Abstract: A surgical retractor device includes at least two retractor blades slidably attached by a tooth and gear mechanism, the blades having concave surfaces facing away from one another. The first concave retractor blade can be joined to a first end of a first bar that has a serrated edge The second concave retractor blade can be joined to a first end of a bar arm that has the gear mechanism at its opposite end. The gear mechanism includes a handle with a gear which causes the first bar to slidably move along the second bar. Each bar can include a housing with a fastener that can receive stabilizers.

Abstract: A surgical retractor device includes at least two retractor blades slidably attached by a tooth and gear mechanism, the blades having concave surfaces facing away from one another. The first concave retractor blade can be joined to a first end of a first bar that has a serrated edge The second concave retractor blade can be joined to a first end of a bar arm that has the gear mechanism at its opposite end. The gear mechanism includes a handle with a gear which causes the first bar to slidably move along the second bar. Each bar can include a housing with a fastener that can receive stabilizers.

Abstract: A universal preservation and transportation device for human organs is disclosed. The device comprises a lower unit and a removable lid that can be attached to the lower unit. A cooling unit and associated power supply can maintain a consistent temperature within the inner compartment, which can be controlled via a control unit and/or remote control. The device also includes a GPS chip for tracking its location.

Abstract: Techniques are disclosed for setting a breakpoint for debugging a neural network. User input is received by a debugger program executable by a host processor indicating a target layer of a neural network at which to halt execution of the neural network. The neural network includes a first set of instructions to be executed by a first execution engine and a second set of instructions to be executed by a second execution engine. A first halt point is set within the first set of instructions and a second halt point is set within the second set of instructions. It is then determined that operation of the first execution engine and the second execution engine has halted. It is then determined that the first execution engine has reached the first halt point. The second execution engine is then caused to move through instructions until reaching the second halt point.

Abstract: Embodiments include techniques for enabling execution of N inferences on an execution engine of a neural network device. Instruction code for a single inference is stored in a memory that is accessible by a DMA engine, the instruction code forming a regular code block. A NOP code block and a reset code block for resetting an instruction DMA queue are stored in the memory. The instruction DMA queue is generated such that, when it is executed by the DMA engine, it causes the DMA engine to copy, for each of N inferences, both the regular code block and an additional code block to an instruction buffer. The additional code block is the NOP code block for the first N?1 inferences and is the reset code block for the Nth inference. When the reset code block is executed by the execution engine, the instruction DMA queue is reset.

Abstract: Techniques are disclosed for setting a breakpoint for debugging a neural network. User input is received by a debugger program executable by a host processor indicating a target layer of a neural network at which to halt execution of the neural network. The neural network includes a first set of instructions to be executed by a first execution engine and a second set of instructions to be executed by a second execution engine. A first halt point is set within the first set of instructions and a second halt point is set within the second set of instructions. It is then determined that operation of the first execution engine and the second execution engine has halted. It is then determined that the first execution engine has reached the first halt point. The second execution engine is then caused to move through instructions until reaching the second halt point.

Abstract: Embodiments include techniques for enabling execution of N inferences on an execution engine of a neural network device. Instruction code for a single inference is stored in a memory that is accessible by a DMA engine, the instruction code forming a regular code block. A NOP code block and a reset code block for resetting an instruction DMA queue are stored in the memory. The instruction DMA queue is generated such that, when it is executed by the DMA engine, it causes the DMA engine to copy, for each of N inferences, both the regular code block and an additional code block to an instruction buffer. The additional code block is the NOP code block for the first N?1 inferences and is the reset code block for the Nth inference. When the reset code block is executed by the execution engine, the instruction DMA queue is reset.

Abstract: An approach for improving throughput for encapsulated network traffic is provided. In an embodiment, a method comprises obtaining a plurality of network addresses of a plurality of intermediaries that facilitate communications between a plurality of virtual machines. A set of source-destination intermediary pairs is determined based on the plurality of network addresses, and for each source-destination intermediary pair, from the set of source-destination intermediary pairs, a precomputed encapsulated header is generated and included in a set of precomputed encapsulated headers.

Abstract: Systems and methods for non-intrusive hardware profiling are provided. In some cases integrated circuit devices can be manufactured without native support for performance measurement and/or debugging capabilities, thereby limiting visibility into the integrated circuit device. Understanding the timing of operations can help to determine whether the hardware of the device is operating correctly and, when the device is not operating correctly, provide information that can be used to debug the device. In order to measure execution time of various tasks performed by the integrated circuit device, program instructions may be inserted to generate notifications that provide tracing information, including timestamps, for operations executed by the integrated circuit device.

Abstract: Described herein are systems, methods, and software to enhance flow operations on a host computing system. In one implementation, a virtual switch on a host identifies a packet from a virtual node. In response to identifying the packet, the virtual switch determines whether the packet corresponds to a cached result action based on traits of the packet. If the packet corresponds to a cached result action, then the virtual switch may process the packet in accordance with the cached result action. In contrast, if the packet does not correspond to a cached result action, then the virtual switch may process the packet in accordance with first flow operations to determine a result action, and cache the result action for use with future packets.

Abstract: Embodiments include techniques for enabling execution of N inferences on an execution engine of a neural network device. Instruction code for a single inference is stored in a memory that is accessible by a DMA engine, the instruction code forming a regular code block. A NOP code block and a reset code block for resetting an instruction DMA queue are stored in the memory. The instruction DMA queue is generated such that, when it is executed by the DMA engine, it causes the DMA engine to copy, for each of N inferences, both the regular code block and an additional code block to an instruction buffer. The additional code block is the NOP code block for the first N?1 inferences and is the reset code block for the Nth inference. When the reset code block is executed by the execution engine, the instruction DMA queue is reset.

Abstract: An approach for improving throughput for encapsulated network traffic is provided. In an embodiment, a method comprises obtaining a plurality of network addresses of a plurality of intermediaries that facilitate communications between a plurality of virtual machines. A set of source-destination intermediary pairs is determined based on the plurality of network addresses, and for each source-destination intermediary pair, from the set of source-destination intermediary pairs, a precomputed encapsulated header is generated and included in a set of precomputed encapsulated headers.

Abstract: An approach for improving throughput for encapsulated network traffic is provided. In an embodiment, a method comprises obtaining a plurality of network addresses of a plurality of intermediaries that facilitate communications between a plurality of virtual machines. A set of source-destination intermediary pairs is determined based on the plurality of network addresses, and for each source-destination intermediary pair, from the set of source-destination intermediary pairs, a precomputed encapsulated header is generated and included in a set of precomputed encapsulated headers.

Abstract: Described herein are systems, methods, and software to enhance flow operations on a host computing system. In one implementation, a virtual switch on a host identifies a packet from a virtual node. In response to identifying the packet, the virtual switch determines whether the packet corresponds to a cached result action based on traits of the packet. If the packet corresponds to a cached result action, then the virtual switch may process the packet in accordance with the cached result action. In contrast, if the packet does not correspond to a cached result action, then the virtual switch may process the packet in accordance with first flow operations to determine a result action, and cache the result action for use with future packets.

Abstract: An approach for improving throughput for encapsulated network traffic is provided. In an embodiment, a method comprises obtaining a plurality of network addresses of a plurality of intermediaries that facilitate communications between a plurality of virtual machines. A set of source-destination intermediary pairs is determined based on the plurality of network addresses, and for each source-destination intermediary pair, from the set of source-destination intermediary pairs, a precomputed encapsulated header is generated and included in a set of precomputed encapsulated headers.

Abstract: A device identifies, based on a program code instruction, an attempted write access operation to a fenced memory slab, where the fenced memory slab includes an alternating sequence of data buffers and guard buffers. The device assigns read-only protection to the fenced slab and invokes, based on the attempted write access operation, a page fault operation. When a faulting address of the attempted write operation is not an address for one of the multiple data buffers, the device performs a panic routine. When the faulting address of the attempted write operation is an address for one of the multiple data buffers, the device removes the read-only protection for the fenced slab and performs a single step processing routine for the program code instruction.

Abstract: In general, techniques are described for providing thread-level tracing within an operating system kernel. A computing device comprising processes, an operating system and a control unit that executes the operating system may implement the techniques. Each of the processes comprises an instance of an application program. Each of the processes comprises one or more separate threads of instruction execution. The operating system concurrently executes the processes. The control unit traces execution of a system call issued to the operating system by one of the threads currently being executed by the control unit to generate a trace log that traces execution of the system call by the operating system without tracing execution of any other ones of the one or more threads corresponding to those of the plurality of processes that are also being executed by the operating system during execution of the system call.

Abstract: A device identifies, based on a program code instruction, an attempted write access operation to a fenced memory slab, where the fenced memory slab includes an alternating sequence of data buffers and guard buffers. The device assigns read-only protection to the fenced slab and invokes, based on the attempted write access operation, a page fault operation. When a faulting address of the attempted write operation is not an address for one of the multiple data buffers, the device performs a panic routine. When the faulting address of the attempted write operation is an address for one of the multiple data buffers, the device removes the read-only protection for the fenced slab and performs a single step processing routine for the program code instruction.

Abstract: A device identifies, based on a program code instruction, an attempted write access operation to a fenced memory slab, where the fenced memory slab includes an alternating sequence of data buffers and guard buffers. The device assigns read-only protection to the fenced slab and invokes, based on the attempted write access operation, a page fault operation. When a faulting address of the attempted write operation is not an address for one of the multiple data buffers, the device performs a panic routine. When the faulting address of the attempted write operation is an address for one of the multiple data buffers, the device removes the read-only protection for the fenced slab and performs a single step processing routine for the program code instruction.