Abstract: A semiconductor package substrate (11) has an array of package sites (13, 14, 16, and 21) that are substantially identical. The entire array of package sites (13, 14, 16, and 21) is covered by an encapsulant (19). The individual package sites (13, 14, 16, and 21) are singulated by sawing through the encapsulant (19) and the underlying semiconductor package substrate (11).

Abstract: A process for manufacturing a semiconductor device (70) using selective plating and etching to form the packaging for such device. A flat sheet (20) of conductive material is selectively plated with a conductive etch resistant material to form a plurality of die attach areas (22) on one side (23) of the sheet (20) and to define die contact (24) and lead contact (26) areas on the opposite side (27) of the sheet. Mold locks (34) which also serve as interconnect bonding areas are selectively plated on the side (23) of the sheet in association with each of the die attach areas (22). Semiconductor die (40) are attached to each of the die attach areas (22) and bonded (42) to the tops of the mold locks (34). A unitary molded resin housing (50) is formed overlying all of the semiconductor device die (40). The underside (27) of the conductive sheet (20) is selectively etched using the plated etch resistant material (24), (26) as an etch mask to form isolated die contact areas (60) and lead contact areas (62).

Abstract: A semiconductor package substrate (10) has an array of package sites (13,14,16,21,22, and 23) that are substantially identical. The entire array of package sites (13,14,16,21,22, and 23) is covered by an encapsulant (19). The individual package sites (13,14,16,21,22, and 23) are singulated by sawing through the encapsulant (19) and the underlying semiconductor package substrate (10).

Abstract: A Micro-Electromechanical Systems (MEMS) device (100) having conductively filled vias (141). A MEMS component (124) is formed on a substrate (110). The substrate has conductively filled vias (140) extending therethrough. The MEMS component (124) is electrically coupled to the conductively filled vias (140). The MEMS component (124) is covered by a protective cap (150). An electrical interconnect (130) is formed on a bottom surface of the substrate (110) for transmission of electrical signals to the MEMS component (124), rather than using wirebonds.

Abstract: A semiconductor package substrate (10) has an array of package sites (13,14,16,21,22, and 23) that are substantially identical. The entire array of package sites (13,14,16,21,22, and 23) is covered by an encapsulant (19). The individual package sites (13,14,16,21,22, and 23) are singulated by sawing through the encapsulant (19) and the underlying semiconductor package substrate (10).

Abstract: A substantially planar insulating sheet of high temperature printed circuit board material (11) is used to form a leadframe strip (18, 19, 21) for a semiconductor package (20). The leadframe strip (18, 19, 21) includes a die attach opening (12) through the insulating sheet (11). A plurality of metallized areas (13, 22, 23) on the insulating sheet (11) form bonding pads (13) and package leads (22). Conductive holes (14) electrically connect the bonding pads (13) and the package leads (22).

Abstract: An improved high frequency high power transistor assembly capable of delivering 600 watts or more at 100 MHz and higher without the need for water cooling is described. Four transistor die individually mounted on separate BeO ceramic isolators are installed in a recessed cavity in a copper base. The BeO isolators have metallized top surfaces which connect to the backside output contacts of the transistor die and extend toward the centerline of the cavity. They connect to a longitudally arranged input-output assembly centrally located over the center line of the cavity. The input-output assembly has a wrap-around electrode structure which brings the transistor output connections to the upper surface of the assembly for easy bonding to the output leads. The input to the individual die is via individual ballast resistors mounted on the input-output assembly, one per transistor, to provide transistor-to-transistor matching for more uniform current distribution.