Abstract: A silicon carrier space transformer assembly includes one or more silicon structures, which provide space transformer scaling to permit interconnection for fine pitch input/output interconnections with a semiconductor die or wafer, and fine pitch test probe tips connected to the one or more silicon structures.

Abstract: A silicon carrier space transformer assembly includes one or more silicon structures, which provide space transformer scaling to permit interconnection for fine pitch input/output interconnections with a semiconductor die or wafer, and fine pitch test probe tips connected to the one or more silicon structures.

Abstract: Techniques for bond pad fabrication are provided. In one aspect, a method of forming a bond pad comprises the following steps. At least one alloying element is selectively introduced to at least a portion of at least one surface of the bond pad. The at least one alloying element is diffused into at least a portion of the bond pad through one or more thermal cycles. The at least one alloying element may be selectively introduced to the bond pad by depositing an alloying element layer comprising the at least one alloying element onto the bond pad and patterning and etching at least a portion of the layer.

Abstract: A silicon carrier space transformer assembly includes one or more silicon structures, which provide space transformer scaling to permit interconnection for fine pitch input/output interconnections with a semiconductor die or wafer, and fine pitch test probe tips connected to the one or more silicon structures.

Abstract: Techniques for bond pad fabrication are provided. In one aspect, a method of forming a bond pad comprises the following steps. At least one alloying element is selectively introduced to at least a portion of at least one surface of the bond pad. The at least one alloying element is diffused into at least a portion of the bond pad through one or more thermal cycles. The at least one alloying element may be selectively introduced to the bond pad by depositing an alloying element layer comprising the at least one alloying element onto the bond pad and patterning and etching at least a portion of the layer.

Abstract: A silicon carrier space transformer assembly includes one or more silicon structures, which provide space transformer scaling to permit interconnection for fine pitch input/output interconnections with a semiconductor die or wafer, and fine pitch test probe tips connected to the one or more silicon structures.

Abstract: A method to fabricate a high density, minimal pitch, thermally matched contactor assembly to maintain electrical contact with contact regions on fully processed semiconductors, preferably while still in wafer form, and throughout a range of temperatures. A guide plate and a contactor assembly for such use, comprising a substrate formed of a material having a coefficient of thermal expansion approximately equal to that of the device; and at least one hole in the guide plate for receiving an electrical contact (probe element) for contacting at least one respective region on said surface, said at least one hole being sized and shaped so as to accept said electrical contact, while allowing said electrical contact (probe element) to move with respect to said hole in said guide plate. The material can be one of silicon, borosilicate glass and cordierite.

Abstract: A durable chip pad for integrated circuit (IC) chips, semiconductor wafer with IC chips with durable chip pads in a number of die locations and a method of making the IC chips on the wafer. The chip may be probed for performance testing with the probe contacting the durable chip pads directly.

Abstract: Techniques for bond pad fabrication are provided. In one aspect, a method of forming a bond pad comprises the following steps. At least one alloying element is selectively introduced to at least a portion of at least one surface of the bond pad. The at least one alloying element is diffused into at least a portion of the bond pad through one or more thermal cycles. The at least one alloying element may be selectively introduced to the bond pad by depositing an alloying element layer comprising the at least one alloying element onto the bond pad and patterning and etching at least a portion of the layer.

Abstract: A method for forming a space transformer (and a space transformer formed by the method) having a first plate and a second plate, the plates being separated by a frame, and electrical connectors for providing electrical connections between electrical contacts which are relatively closely spaced on the first plate and relatively more widely spaced on the second plate. The method comprises attaching first ends of wires to first electrically conductive regions on the first plate; forming insulating layers over the wires; forming electrically conductive coverings over the insulating layers; and connecting second ends of the wires to second electrically conductive regions on the second plate.

Abstract: A durable chip pad for integrated circuit (IC) chips, semiconductor wafer with IC chips with durable chip pads in a number of die locations and a method of making the IC chips on the wafer. The chip may be probed for performance testing with the probe contacting the durable chip pads directly.

Abstract: Disclosed is a reinforced bond pad structure having nonplanar dielectric structures and a metallic bond layer conformally formed over the nonplanar dielectric structures. The nonplanar dielectric structures are substantially reproduced in the metallic bond layer so as to form nonplanar metallic structures. Surrounding each of the nonplanar metallic structures is a ring of dielectric material which provides a hard stop during probing of the bond pad so as to limit the amount of bond pad that can be removed during probing.

Abstract: A semiconductor device, and a method of fabricating the device, having a copper wiring level and an aluminum bond pad above the copper wiring level. In addition to a barrier layer which is normally present to protect the copper wiring level, there is a composite layer between the aluminum bond pad and the barrier layer to make the aluminum bond pad more robust so as to withstand the forces of bonding and probing. The composite layer is a sandwich of a refractory metal and a refractory metal nitride.

Abstract: A bond pad structure for an integrated circuit has a bond pad with an operational bonding area for receiving a bonded wire thereon. A test probe contacting area, extends from the operational bonding area, with the test probe contact area being electrically contiguous with the operational bonding area. In a preferred embodiment of the invention, the test probe contacting area has a surface area which is less than the surface area corresponding to the operational bonding area.