Abstract: The disclosure provides a method including: identifying a fill-dense region of an integrated circuit (IC) layout having a plurality of fill cells, and a target fill region of the IC layout adjacent to the fill-dense region and free of fill cells; modifying the IC layout by removing a fill cell from the fill-dense region and inserting a duplicate of the removed fill cell within the target fill region to at least partially fill the target fill region; and providing instructions to manufacture an IC using the modified IC layout. The method may reduce a feature density of the fill-dense region to less than an allowable feature density, while adding fill features to otherwise unfillable regions.

Abstract: The disclosure provides a method including: identifying a fill-dense region of an integrated circuit (IC) layout having a plurality of fill cells, and a target fill region of the IC layout adjacent to the fill-dense region and free of fill cells; modifying the IC layout by removing a fill cell from the fill-dense region and inserting a duplicate of the removed fill cell within the target fill region to at least partially fill the target fill region; and providing instructions to manufacture an IC using the modified IC layout. The method may reduce a feature density of the fill-dense region to less than an allowable feature density, while adding fill features to otherwise unfillable regions.