Patents by Inventor Samuel Pan

Samuel Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180190804
    Abstract: A tunneling field-effect transistor includes: 1) a source region; 2) a drain region; 3) a channel region extending between the source region and the drain region; 4) a gate electrode spaced from the channel region; and 5) a dielectric layer disposed between the gate electrode and the channel region. The gate electrode includes a first section including a first conductive material M1 and a second section including a different, second conductive material M2, and the first section is electrically connected to the second section.
    Type: Application
    Filed: June 30, 2016
    Publication date: July 5, 2018
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Chi On CHUI, Andrew Samuel PAN
  • Patent number: 6576511
    Abstract: A semiconductor substrate having a source/drain region is initially provided, wherein a channel is formed in the space between the source/drain region within the semiconductor substrate. Then the oxide-nitride-oxide layers are formed on the semiconductor substrate, wherein the nitride layer is a charge trapping layer. Afterward, an electrically conductive material layer such as a gate is formed on and overlays the oxide-nitride-oxide layers. Subsequently, the memory cell is programmed by ultraviolet light irradiation to increase the threshold voltage of the memory cell.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: June 10, 2003
    Assignee: Macronix International Co., Ltd.
    Inventors: Samuel Pan, Chia-Hsing Chen, Chun-Jung Lin, Minnie Hsiung
  • Publication number: 20030089935
    Abstract: A non-volatile semiconductor memory device with a multi-layer gate insulating structure is provided. The non-volatile semiconductor memory device comprises a gate insulating structure formed between a gate and a channel region, which includes a top silicon nitride layer, an intermediate silicon nitride layer and a bottom silicon nitride layer. When an electric field is applied between the gate and a drain region beside the channel region, hot carriers exhibit a direct tunneling across the bottom silicon nitride layer from the drain region for a write-erase operation. The hot carriers having exhibited the direct tunneling from the drain region are trapped into the intermediate silicon nitride layer.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 15, 2003
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Tso-Hung Fan, Tao-Cheng Lu, Samuel Pan, Ta-Hui Wang
  • Patent number: 6512696
    Abstract: A method of programming and erasing a SNNNS type non-volatile memory cell is provided. The programming operation is performed by channel hot electron injection from a drain side to an intermediate silicon nitride layer. The erasing operation is performed by channel hot hole injection from a drain side to an intermediate silicon nitride layer. The SNNNS type non-volatile memory cell provides highly efficient hot carrier injection under low applied voltages, both for programming and erasing operations. Thus, the present method provides improved performance characteristics such as shorter programming/erasing times and lower applied voltages.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: January 28, 2003
    Assignee: Macronix International Co., Ltd.
    Inventors: Tso-Hung Fan, Tao-Cheng Lu, Samuel Pan, Ta-Hui Wang
  • Publication number: 20020164855
    Abstract: First of all, a semiconductor substrate having a source/drain region is provided, wherein a channel being formed in the space between the source/drain region within the semiconductor substrate. Then the oxide-nitride-oxide layers are formed on the semiconductor substrate, wherein the nitride layer is a charge trapping layer. Afterward, an electrically conductive material layer as a gate is formed on and overlaying the oxide-nitride-oxide layers. Subsequently, the memory cell is programmed by ultraviolet light irradiation to increase threshold voltage of the memory cell.
    Type: Application
    Filed: May 2, 2001
    Publication date: November 7, 2002
    Inventors: Samuel Pan, Chia-Hsing Chen, Chun-Jung Lin, Minnie Hsiung
  • Patent number: 6444523
    Abstract: A fabrication method for a memory device with a floating gate is provided. A substrate is provided. A channel doping step is performed on the substrate, wherein the actual threshold voltage of the subsequently formed memory device becomes greater than the preset threshold voltage. A stack gate and source/drain regions are then sequentially formed on the substrate to complete the formation of the memory device. The drain-turn-on leakage is prevented by an increase of the actual threshold voltage.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: September 3, 2002
    Assignee: Macronix International Co., Ltd.
    Inventors: Tso-Hung Fan, Tao-Cheng Lu, Wen-Jer Tsai, Samuel Pan