Patents by Inventor Samuel Paul Visalli
Samuel Paul Visalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11119909Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.Type: GrantFiled: October 2, 2019Date of Patent: September 14, 2021Assignee: Texas Instmments IncorporatedInventors: Denis Roland Beaudoin, Ritesh Dhirajlal Sojitra, Samuel Paul Visalli
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Patent number: 11094392Abstract: A system-on-chip includes first and second devices. An interconnect segment couples between the first and second devices. A bridge is coupled between the first and second devices and coupled to the interconnect segment. At least one of the bridge or interconnect segment include first and second multiplexers, a monitor circuit, and exclusive-OR logic. The first multiplexer has first and second multiplexer inputs and a first multiplexer output. The second multiplexer has third and fourth multiplexer inputs and a second multiplexer output. The monitor circuit has a first and second monitor circuit outputs. The first monitor circuit output is coupled to the second multiplexer input and the second monitor circuit output is coupled to the fourth multiplexer input. The exclusive-OR logic has first and second exclusive-OR logic inputs. The first exclusive-OR logic input couples to the first multiplexer output and the second exclusive-OR logic input couples to the second multiplexer output.Type: GrantFiled: October 14, 2019Date of Patent: August 17, 2021Assignee: Texas Instruments IncorporatedInventors: Charles Lance Fuoco, Brian Karguth, Jay Bryan Reimer, Samuel Paul Visalli
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Publication number: 20210208189Abstract: In described examples, an SoC includes at least two voltage domains interconnected with a communication bus. Detection logic in a first voltage domain determines when a voltage error occurs in a second voltage domain and isolates communication via the communication bus when a voltage error or a timing error is detected.Type: ApplicationFiled: December 18, 2020Publication date: July 8, 2021Inventors: Jose Luis Flores, Ramakrishnan Venkatasubramanian, Samuel Paul Visalli
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Publication number: 20210073150Abstract: An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.Type: ApplicationFiled: November 17, 2020Publication date: March 11, 2021Inventors: Brian Jason KARGUTH, Charles Lance FUOCO, Samuel Paul VISALLI, Michael Anthony DENIO
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Publication number: 20210055991Abstract: A data storage circuit includes memory, an error correcting code (ECC) storage circuit, and control circuitry. The memory is configured to store a data value comprising a plurality of fields. Each of the fields is independently writable. The ECC storage circuit is configured to store an ECC value corresponding to the data value. The control circuitry is configured to receive a field value to be written into one of the fields, and store the field value in the one of the fields by writing only the field value to the memory. The control circuitry is also configured to retrieve the ECC value from the ECC storage circuit, compute an updated ECC value based on the ECC value retrieved from the ECC storage circuit and the field value, and store the updated ECC value in the ECC storage circuit.Type: ApplicationFiled: October 26, 2020Publication date: February 25, 2021Inventor: Samuel Paul VISALLI
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Patent number: 10853170Abstract: A data storage circuit includes memory, an error correcting code (ECC) storage circuit, and control circuitry. The memory is configured to store a data value comprising a plurality of fields. Each of the fields is independently writable. The ECC storage circuit is configured to store an ECC value corresponding to the data value. The control circuitry is configured to receive a field value to be written into one of the fields, and store the field value in the one of the fields by writing only the field value to the memory. The control circuitry is also configured to retrieve the ECC value from the ECC storage circuit, compute an updated ECC value based on the ECC value retrieved from the ECC storage circuit and the field value, and store the updated ECC value in the ECC storage circuit.Type: GrantFiled: September 6, 2018Date of Patent: December 1, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Samuel Paul Visalli
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Patent number: 10838896Abstract: An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.Type: GrantFiled: October 14, 2019Date of Patent: November 17, 2020Assignee: Texas Instruments IncorporatedInventors: Brian Jason Karguth, Charles Lance Fuoco, Samuel Paul Visalli, Michael Anthony Denio
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Publication number: 20200183826Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.Type: ApplicationFiled: October 2, 2019Publication date: June 11, 2020Inventors: Denis Roland BEAUDOIN, Ritesh Dhirajlal SOJITRA, Samuel Paul VISALLI
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Publication number: 20200117626Abstract: An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.Type: ApplicationFiled: October 14, 2019Publication date: April 16, 2020Inventors: Brian Jason KARGUTH, Charles Lance FUOCO, Samuel Paul VISALLI, Michael Anthony DENIO
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Publication number: 20200118642Abstract: A system-on-chip includes first and second devices. An interconnect segment couples between the first and second devices. A bridge is coupled between the first and second devices and coupled to the interconnect segment. At least one of the bridge or interconnect segment include first and second multiplexers, a monitor circuit, and exclusive-OR logic. The first multiplexer has first and second multiplexer inputs and a first multiplexer output. The second multiplexer has third and fourth multiplexer inputs and a second multiplexer output. The monitor circuit has a first and second monitor circuit outputs. The first monitor circuit output is coupled to the second multiplexer input and the second monitor circuit output is coupled to the fourth multiplexer input. The exclusive-OR logic has first and second exclusive-OR logic inputs. The first exclusive-OR logic input couples to the first multiplexer output and the second exclusive-OR logic input couples to the second multiplexer output.Type: ApplicationFiled: October 14, 2019Publication date: April 16, 2020Inventors: Charles Lance FUOCO, Brian KARGUTH, Jay Bryan REIMER, Samuel Paul VISALLI
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Publication number: 20200110132Abstract: A synchronization circuit includes a first synchronizer, a second synchronizer, and selection circuitry. The first synchronizer is configured to synchronize a received signal to a clock signal. The second synchronizer is disposed in parallel with the first synchronizer and configured to synchronize the received signal to the clock signal. The selection circuitry is coupled to the first synchronizer and the second synchronizer. The selection circuitry is configured to provide an output value generated by the first synchronizer at an output terminal of the synchronization circuit based on the output value generated by the first synchronizer being the same as an output value generated by the second synchronizer.Type: ApplicationFiled: October 5, 2018Publication date: April 9, 2020Inventors: Denis Roland BEAUDOIN, Samuel Paul VISALLI
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Publication number: 20200081772Abstract: A data storage circuit includes memory, an error correcting code (ECC) storage circuit, and control circuitry. The memory is configured to store a data value comprising a plurality of fields. Each of the fields is independently writable. The ECC storage circuit is configured to store an ECC value corresponding to the data value. The control circuitry is configured to receive a field value to be written into one of the fields, and store the field value in the one of the fields by writing only the field value to the memory. The control circuitry is also configured to retrieve the ECC value from the ECC storage circuit, compute an updated ECC value based on the ECC value retrieved from the ECC storage circuit and the field value, and store the updated ECC value in the ECC storage circuit.Type: ApplicationFiled: September 6, 2018Publication date: March 12, 2020Inventor: Samuel Paul VISALLI
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Patent number: 8943248Abstract: A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. The bus is monitored for discarded speculative read and for merged write transactions in order to determine the true bus throughputs. Bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, or alternatively by external trigger events.Type: GrantFiled: January 9, 2012Date of Patent: January 27, 2015Assignee: Texas Instruments IncorporatedInventors: Samuel Paul Visalli, Brian Cruickshank, Chunhua Hu
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Patent number: 8706937Abstract: A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Users are alerted to timing problems as they occur, and bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, or alternatively by external trigger events.Type: GrantFiled: December 17, 2011Date of Patent: April 22, 2014Assignee: Texas Instruments IncorporatedInventors: Brian Cruickshank, David Quintin Bell, Samuel Paul Visalli, Chunhua Hu, Akila Subramaniam, Charles Fuoco
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Publication number: 20120226837Abstract: A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Users are alerted to timing problems as they occur, and bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, or alternatively by external trigger events.Type: ApplicationFiled: December 17, 2011Publication date: September 6, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Brian Cruickshank, David Quintin Bell, Samuel Paul Visalli, Chunhua Hu, Akila Subramaniam, Charles Fuoco
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Publication number: 20120226839Abstract: A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Bus transactions to a selected slave are monitored to determine possible conflicts when multiple masters may be addressing the slave. Users are alerted to timing problems as they occur, and bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, by a selected address range or alternatively by external trigger events.Type: ApplicationFiled: January 11, 2012Publication date: September 6, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Charles Fuoco, Brian Cruickshank, Akila Subramaniam, Chunhua Hu, Samuel Paul Visalli
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Publication number: 20120226838Abstract: A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. The bus is monitored for discarded speculative read and for merged write transactions in order to determine the true bus throughputs. Bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, or alternatively by external trigger events.Type: ApplicationFiled: January 9, 2012Publication date: September 6, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Samuel Paul Visalli, Brian Cruickshank, Chunhua Hu