Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure includes a wiring line and a via upon and electrically contacting the wiring line. The via induces lateral etching voids between the via and the wiring line below the via upon the surface of the wiring line. The second circuit structure includes a similar wiring line, relative to the reference wiring line, without or fewer via thereupon. The first circuit structure is therefore relatively more prone to lateral etching void formation as compared to the second circuit structure. Resistances are measured across the first circuit structure and the second circuit structure and compared against a comparison threshold to determine whether the first circuit structure includes one or more lateral etching voids. If the first structure is deemed to not include lateral etching voids, the fabrication process of the device may be deemed reliable.

Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure includes a wiring line and a via upon and electrically contacting the wiring line. The via induces lateral etching voids between the via and the wiring line below the via upon the surface of the wiring line. The second circuit structure includes a similar wiring line, relative to the reference wiring line, without or fewer via thereupon. The first circuit structure is therefore relatively more prone to lateral etching void formation as compared to the second circuit structure. Resistances are measured across the first circuit structure and the second circuit structure and compared against a comparison threshold to determine whether the first circuit structure includes one or more lateral etching voids. If the first structure is deemed to not include lateral etching voids, the fabrication process of the device may be deemed reliable.

Abstract: After forming at least one opening in a material stack comprising a sacrificial metal template layer overlying a first dielectric material layer, a sacrificial material portion is deposited in the at least one opening as a place holder for an interconnect structure later formed. Next, the sacrificial metal template layer is removed and a second dielectric material layer is formed to fill voids that were previously occupied by the sacrificial metal template layer. After removing the sacrificial material portion from the at least one opening, an interconnect structure is formed within the at least one opening.

Abstract: An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by utilizing a graphene-based barrier metal layer to block oxygen intrusion from a dielectric layer into the interconnect structure and block copper diffusion from the interconnect structure into the dielectric layer, are disclosed. At least one opening is formed in a dielectric layer. A graphene-based barrier metal layer disposed on the dielectric layer is formed. A seed layer disposed on the graphene-based barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the graphene-based barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.

Abstract: An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by utilizing a graphene-based barrier metal layer to block oxygen intrusion from a dielectric layer into the interconnect structure and block copper diffusion from the interconnect structure into the dielectric layer, are disclosed. At least one opening is formed in a dielectric layer. A graphene-based barrier metal layer disposed on the dielectric layer is formed. A seed layer disposed on the graphene-based barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the graphene-based barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.

Abstract: An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by utilizing a graphene-based barrier metal layer to block oxygen intrusion from a dielectric layer into the interconnect structure and block copper diffusion from the interconnect structure into the dielectric layer, are disclosed. At least one opening is formed in a dielectric layer. A graphene-based barrier metal layer disposed on the dielectric layer is formed. A seed layer disposed on the graphene-based barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the graphene-based barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.

Abstract: An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by utilizing a graphene-based barrier metal layer to block oxygen intrusion from a dielectric layer into the interconnect structure and block copper diffusion from the interconnect structure into the dielectric layer, are disclosed. At least one opening is formed in a dielectric layer. A graphene-based barrier metal layer disposed on the dielectric layer is formed. A seed layer disposed on the graphene-based barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the graphene-based barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.

Abstract: Disclosed is a process of an integration method to form an air gap in an interconnect. On top of a metal wiring layer on a semiconductor substrate is deposited a dielectric cap layer followed by a sacrificial dielectric layer and pattern transfer layers. A pattern is transferred through the pattern transfer layers, sacrificial dielectric layer, dielectric cap layer and into the metal wiring layer. The presence of the sacrificial dielectric layer aids in controlling the thickness and profile of the dielectric cap layer which in turn affects reliability of the interconnect.