Abstract: Die-to-die electrical interconnects, optical couplers, and related methods for electronic and photonic co-packaging are described. Optical couplers include multi-segmented tapered waveguide core segments, slotted core segments, and graded refractive index structures to significantly relax alignment tolerances between dies. Conductive nanopillars, conductive pads, and conductive micropillars can be used to make electrical connections between circuitry on the interconnected dies. The electrical connections can be used to self-align the optical couplers between the dies. Due to relaxed optical alignment tolerances, electrical interconnects and optical coupling between dies can be made in the same die-to-die bonding step.

Abstract: Optical interconnects can offer higher bandwidth, lower power, lower cost, and higher latency than electrical interconnects alone. The optical interconnect system enables both optical and electrical interconnection, leverages existing fabrication processes to facilitate package-level integration, and delivers high alignment tolerance and low coupling losses. The optical interconnect system provides connections between a photonics integrated chip (PIC) and a chip carrier and between the chip carrier and external circuitry. The system provides a single flip chip interconnection between external circuitry and a chip carrier using a ball grid array (BGA) infrastructure. The system uses graded index (GRIN) lenses and cross-taper waveguide couplers to optically couple components, delivers coupling losses of less than 0.5 dB with an alignment tolerance of ±1 ?m, and accommodates a 2.5× higher bandwidth density.

Abstract: Optical interconnects can offer higher bandwidth, lower power, lower cost, and higher latency than electrical interconnects alone. The optical interconnect system enables both optical and electrical interconnection, leverages existing fabrication processes to facilitate package-level integration, and delivers high alignment tolerance and low coupling losses. The optical interconnect system provides connections between a photonics integrated chip (PIC) and a chip carrier and between the chip carrier and external circuitry. The system provides a single flip chip interconnection between external circuitry and a chip carrier using a ball grid array (BGA) infrastructure. The system uses graded index (GRIN) lenses and cross-taper waveguide couplers to optically couple components, delivers coupling losses of less than 0.5 dB with an alignment tolerance of ±1 ?m, and accommodates a 2.5× higher bandwidth density.