Abstract: An integrated circuit includes a field effect transistor (FET) and a phase change memory (PCM) cell. The PCM cell includes a heater, wherein a bottom surface of the heater is at or below a top surface of the FET.

Abstract: A phase change material (PCM) memory cell having a metal heater element of sub-EUV dimension. The PCM memory cell includes a bottom electrode of a metal-containing material, a memory cell structure including a phase change material; and a metal heater element of sub-extreme ultraviolet (sub-EUV) dimension situated between and electrically connecting the bottom electrode and PCM memory cell structure. The metal heater element is formed of a circular via structure of sub-EUV dimension and has a seamless metal-nitride fill material. The circular via structure of sub-extreme ultraviolet (sub-EUV) dimension further includes a metal-nitride liner of sub-EUV dimension, the metal-nitride liner of sub-EUV dimension including a thicker metal-nitride liner bottom surface portion and thinner sidewall metal-nitride portions. The thicker metal-nitride liner bottom surface portion improves heat insulation and provides for high resistance/low power switching and reduced amorphous phase change material volumes.

Abstract: A vertical field effect transistor includes a top source/drain region in contact with a top portion of a channel fin extending perpendicularly from a semiconductor substrate, a bottom source/drain region is disposed above the semiconductor substrate and on opposite sidewalls of a bottom portion of the channel fin, a metal gate surrounding the channel fin is separated from the top source/drain region by a top spacer and from the bottom source/drain region by a bottom spacer, the metal gate and the top spacer are in contact with an adjacent first interlevel dielectric layer. A silicide layer is directly above an uppermost surface of the top source/drain region, and a nitride layer is directly above an uppermost surface of the silicide layer. A top source/drain contact, having a size that is substantially less than a length of the channel fin, extends until an uppermost surface of the nitride layer.

Abstract: A vertical field effect transistor includes a top source/drain region in contact with a top portion of a channel fin extending perpendicularly from a semiconductor substrate, a bottom source/drain region is disposed above the semiconductor substrate and on opposite sidewalls of a bottom portion of the channel fin, a metal gate surrounding the channel fin is separated from the top source/drain region by a top spacer and from the bottom source/drain region by a bottom spacer, the metal gate and the top spacer are in contact with an adjacent first interlevel dielectric layer. A silicide layer is directly above an uppermost surface of the top source/drain region, and a nitride layer is directly above an uppermost surface of the silicide layer. A top source/drain contact, having a size that is substantially less than a length of the channel fin, extends until an uppermost surface of the nitride layer.

Abstract: Embodiments of the invention are directed to a method that includes forming a dielectric region having a dielectric region top surface, wherein the dielectric top surface is substantially planar. A first interconnect structure having a substantially planar interconnect structure top surface with unintended non-planar regions is formed in the dielectric region.

Abstract: Embodiments of the invention are directed to a method that includes forming a dielectric region having a dielectric region top surface, wherein the dielectric top surface is substantially planar. A first interconnect structure having a substantially planar interconnect structure top surface with unintended non-planar regions is formed in the dielectric region.

Abstract: A fuse structure includes within an aperture within a dielectric layer located over a substrate that exposes a conductor contact layer within the substrate a seed layer interposed between the conductor contact layer and another conductor layer. The seed layer includes a doped copper material that includes a dopant immobilized predominantly within the seed layer. The fuse structure may be severed while not severing a conductor interconnect structure also located over the substrate that exposes a second conductor contact layer within a second aperture. In contrast with the fuse structure that includes the doped seed layer having the immobilized dopant, the interconnect structure includes a doped seed layer having a mobile dopant.

Abstract: A method and structure for transferring a lithographic pattern into a substrate includes forming a dielectric hardmask layer over a dielectric substrate. A metal hardmask layer is formed over the dielectric hardmask layer. A protective capping hardmask layer or capping film is formed over the metal hardmask layer, and a lithographic structure for pattern transfer is formed over the capping layer. A pattern is transferred into the dielectric substrate using the defined lithographic structure. The capping hardmask layer can be removed during subsequent processing.

Abstract: A fuse structure includes within an aperture within a dielectric layer located over a substrate that exposes a conductor contact layer within the substrate a seed layer interposed between the conductor contact layer and another conductor layer. The seed layer includes a doped copper material that includes a dopant immobilized predominantly within the seed layer. The fuse structure may be severed while not severing a conductor interconnect structure also located over the substrate that exposes a second conductor contact layer within a second aperture. In contrast with the fuse structure that includes the doped seed layer having the immobilized dopant, the interconnect structure includes a doped seed layer having a mobile dopant.

Abstract: A method and structure for transferring a lithographic pattern into a substrate includes forming a dielectric hardmask layer over a dielectric substrate. A metal hardmask layer is formed over the dielectric hardmask layer. A protective capping hardmask layer or capping film is formed over the metal hardmask layer, and a lithographic structure for pattern transfer is formed over the capping layer. A pattern is transferred into the dielectric substrate using the defined lithographic structure. The capping hardmask layer can be removed during subsequent processing.