Patents by Inventor Samuel Tiller
Samuel Tiller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7180349Abstract: A frequency divider circuit for providing a divided clock signal having a frequency that is an odd integer factor less than the frequency of an incoming system clock signal. The frequency divider includes a clock generator circuit coupled to a delay circuit which operates in an active and a reset phase to provide a divided clock signal from the system clock signal. In the active phase, the clock generator circuit drives the divided clock signal to a first logic state until a reset signal is received. The delay circuit then generates the reset signal at a predetermined number of system clock edges after the divided clock signal is driven to the first logic state. In the reset phase, both the clock generator circuit and the delay circuit are reset in response to the reset signal such that the clock generator circuit immediately drives the divided clock signal to a second logic state, and the delay circuit disables the reset signal within the predetermined number of system clock edges.Type: GrantFiled: October 6, 2005Date of Patent: February 20, 2007Assignee: Research In Motion LimitedInventors: Curtis R. Leifso, Samuel A. Tiller
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Publication number: 20060028251Abstract: A frequency divider circuit for providing a divided clock signal having a frequency that is an odd integer factor less than the frequency of an incoming system clock signal. The frequency divider includes a clock generator circuit coupled to a delay circuit which operates in an active and a reset phase to provide a divided clock signal from the system clock signal. In the active phase, the clock generator circuit drives the divided clock signal to a first logic state until a reset signal is received. The delay circuit then generates the reset signal at a predetermined number of system clock edges after the divided clock signal is driven to the first logic state. In the reset phase, both the clock generator circuit and the delay circuit are reset in response to the reset signal such that the clock generator circuit immediately drives the divided clock signal to a second logic state, and the delay circuit disables the reset signal within the predetermined number of system clock edges.Type: ApplicationFiled: October 6, 2005Publication date: February 9, 2006Inventors: Curtis Leifso, Samuel Tiller
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Patent number: 6992513Abstract: A frequency divider circuit for providing a divided clock signal having a frequency that is an odd integer factor less than the frequency of an incoming system clock signal. The frequency divider includes a clock generator circuit coupled to a delay circuit which operates in an active and a reset phase to provide a divided clock signal from the system clock signal. In the active phase, the clock generator circuit drives the divided clock signal to a first logic state until a reset signal is received. The delay circuit then generates the reset signal at a predetermined number of system clock edges after the divided clock signal is driven to the first logic state. In the reset phase, both the clock generator circuit and the delay circuit are reset in response to the reset signal such that the clock generator circuit immediately drives the divided clock signal to a second logic state, and the delay circuit disables the reset signal within the predetermined number of system clock edges.Type: GrantFiled: November 10, 2004Date of Patent: January 31, 2006Assignee: Research In Motion LimitedInventors: Curtis R. Leifso, Samuel A. Tiller
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Publication number: 20050127959Abstract: A frequency divider circuit for providing a divided clock signal having a frequency that is an odd integer factor less than the frequency of an incoming system clock signal. The frequency divider includes a clock generator circuit coupled to a delay circuit which operates in an active and a reset phase to provide a divided clock signal from the system clock signal. In the active phase, the clock generator circuit drives the divided clock signal to a first logic state until a reset signal is received. The delay circuit then generates the reset signal at a predetermined number of system clock edges after the divided clock signal is driven to the first logic state. In the reset phase, both the clock generator circuit and the delay circuit are reset in response to the reset signal such that the clock generator circuit immediately drives the divided clock signal to a second logic state, and the delay circuit disables the reset signal within the predetermined number of system clock edges.Type: ApplicationFiled: November 10, 2004Publication date: June 16, 2005Inventors: Curtis Leifso, Samuel Tiller
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Patent number: 6897734Abstract: A device for providing the functionality of an oscillator and mixer is disclosed herein. The device uses a differential pair to provide first and second filter networks with a time varying signal. The first filer network generates an oscillating signal through the use of a generated negative resistance and provides the oscillating signal while filtering out unwanted signals. The second filter network receives the time varying input signal and the oscillating signal and provides a mixed output while preventing the transmission of oscillations at the oscillating signal frequency. A double balanced embodiment is also disclosed.Type: GrantFiled: October 23, 2003Date of Patent: May 24, 2005Assignee: Research In Motion LimitedInventor: Samuel A. Tiller
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Patent number: 6870425Abstract: A gain control circuit that permits a variable gain amplifier circuit to operate with high input linearity and low power consumption is disclosed. The variable gain amplifier includes a standard differential bipolar transistor input circuit and a pair of degeneration transistors connected to a current source transistor. The gain control circuit provides a variable degeneration control voltage to vary the effective resistance of the degeneration transistors and a variable bias voltage to vary the current of the current source transistor. The input linearity of the variable gain amplifier is controlled independently of gain by adjusting the effective resistance and the current in an inverse relationship such that at maximum gain the current is at a maximum while the degeneration resistance is at a minimum, and at minimum gain the current is at a minimum while the degeneration resistance is at a maximum.Type: GrantFiled: April 16, 2003Date of Patent: March 22, 2005Assignee: Research in Motion LimitedInventors: Curtis R. Leifso, Samuel A. Tiller
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Patent number: 6864754Abstract: A device for providing the functionality of an oscillator and mixer is disclosed herein. The device uses a differential pair to provide first and second filter networks with a time varying signal. The first filter network generates an oscillating signal through the use of a generated negative resistance and provides the oscillating signal while filtering out unwanted signals. The second filter network receives the time varying input signal and the oscillating signal and provides a mixed output while preventing the transmission of oscillations at the oscillating signal frequency. A double balanced embodiment is also disclosed.Type: GrantFiled: September 25, 2002Date of Patent: March 8, 2005Assignee: Research In Motion LimitedInventor: Samuel A. Tiller
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Patent number: 6847239Abstract: A frequency divider circuit for providing a divided clock signal having a frequency that is an odd integer factor less than the frequency of an incoming system clock signal. The frequency divider includes a clock generator circuit coupled to a delay circuit which operates in an active and a reset phase to provide a divided clock signal from the system clock signal. In the active phase, the clock generator circuit drives the divided clock signal to a first logic state until a reset signal is received. The delay circuit then generates the reset signal at a predetermined number of system clock edges after the divided clock signal is driven to the first logic state. In the reset phase, both the clock generator circuit and the delay circuit are reset in response to the reset signal such that the clock generator circuit immediately drives the divided clock signal to a second logic state, and the delay circuit disables the reset signal within the predetermined number of system clock edges.Type: GrantFiled: April 16, 2003Date of Patent: January 25, 2005Assignee: Research In Motion LimitedInventors: Curtis R. Leifso, Samuel A. Tiller
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Publication number: 20040092244Abstract: A device for providing the functionality of an oscillator and mixer is disclosed herein. The device uses a differential pair to provide first and second filter networks with a time varying signal. The first filer network generates an oscillating signal through the use of a generated negative resistance and provides the oscillating signal while filtering out unwanted signals. The second filter network receives the time varying input signal and the oscillating signal and provides a mixed output while preventing the transmission of oscillations at the oscillating signal frequency. A double balanced embodiment is also disclosed.Type: ApplicationFiled: October 23, 2003Publication date: May 13, 2004Applicant: Research In Motion LimitedInventor: Samuel A. Tiller
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Publication number: 20030193355Abstract: A frequency divider circuit for providing a divided clock signal having a frequency that is an odd integer factor less than the frequency of an incoming system clock signal. The frequency divider includes a clock generator circuit coupled to a delay circuit which operates in an active and a reset phase to provide a divided clock signal from the system clock signal. In the active phase, the clock generator circuit drives the divided clock signal to a first logic state until a reset signal is received. The delay circuit then generates the reset signal at a predetermined number of system clock edges after the divided clock signal is driven to the first logic state. In the reset phase, both the clock generator circuit and the delay circuit are reset in response to the reset signal such that the clock generator circuit immediately drives the divided clock signal to a second logic state, and the delay circuit disables the reset signal within the predetermined number of system clock edges.Type: ApplicationFiled: April 16, 2003Publication date: October 16, 2003Inventors: Curtis R. Leifso, Samuel A. Tiller
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Publication number: 20030193370Abstract: A gain control circuit that permits a variable gain amplifier circuit to operate with high input linearity and low power consumption is disclosed. The variable gain amplifier includes a standard differential bipolar transistor input circuit and a pair of degeneration transistors connected to a current source transistor. The gain control circuit provides a variable degeneration control voltage to vary the effective resistance of the degeneration transistors and a variable bias voltage to vary the current of the current source transistor. The input linearity of the variable gain amplifier is controlled independently of gain by adjusting the effective resistance and the current in an inverse relationship such that at maximum gain the current is at a maximum while the degeneration resistance is at a minimum, and at minimum gain the current is at a minimum while the degeneration resistance is at a maximum.Type: ApplicationFiled: April 16, 2003Publication date: October 16, 2003Inventors: Curtis R. Leifso, Samuel A. Tiller
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Publication number: 20030071693Abstract: A device for providing the functionality of an oscillator and mixer is disclosed herein. The device uses a differential pair to provide first and second filter networks with a time varying signal. The first filer network generates an oscillating signal through the use of a generated negative resistance and provides the oscillating signal while filtering out unwanted signals. The second filter network receives the time varying input signal and the oscillating signal and provides a mixed output while preventing the transmission of oscillations at the oscillating signal frequency. A double balanced embodiment is also disclosed.Type: ApplicationFiled: September 25, 2002Publication date: April 17, 2003Applicant: Research In Motion LimitedInventor: Samuel A. Tiller
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Patent number: 5896062Abstract: In an amplifier circuit, bias feedback to an amplifying transistor is provided by interconnecting the DC bias voltage applied to the transistor output and the transistor input with a feedback circuit consisting of a switching transistor and bias resistors. Bias current and stable operation is provided by this design. In a particular embodiment two common emitter amplifying transistors are connected to a common output and each has a separate bias feedback circuit including a respective switching transistor. A single DC control input connected to the inputs of both switching transistors can be used to switch between the two amplifying transistors depending on the value of the control voltage thereby amplifying either an input signal of the first amplifying transistor or an input signal of the second amplifying transistor.Type: GrantFiled: March 21, 1997Date of Patent: April 20, 1999Assignee: Northern Telecom LimitedInventors: Samuel A. Tiller, Stephen G. Roy
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Patent number: 5365138Abstract: A double mode surface wave resonator comprises two IDTs (inter-digital transducers), arranged side by side between reflection gratings, on a surface of a piezoelectric substrate to provide for coupling of surface waves therebetween, each IDT having interleaved electrodes extending from a common rail between the two IDTs and from a respective outer rail of the IDT. One or each of the IDTs and its outer rail is divided into two halves for providing a differential signal connection to the resonator. The electrodes of the IDTs can be arranged in spatial synchronism with adjacent fingers of the reflection gratings to reduce spurious longitudinal modes.Type: GrantFiled: December 2, 1993Date of Patent: November 15, 1994Assignee: Northern Telecom LimitedInventors: John C. B. Saw, Thomas P. Cameron, Mark S. Suthers, John J. Nisbet, Samuel A. Tiller