Abstract: Disclosed is a manufacturing method of forming silicon gate, self-aligned MOS-type devices having submicron dimensions. After forming the gate from a highly doped polysilicon layer using a mask, the structure is subjected to a low temperature (700-750 degrees C.) thermal oxidation. Due to enhanced oxidation rate of doped silicon surfaces, a very thick oxide layer over the polysilicon gate sidewalls and a relatively thin oxide layer over the source-drain regions of the substrate are formed. The mask over the polysilicon and the oxide layer over the source-drain regions is removed and source-drain implantation is accomplished followed by selective deposition of metal (e.g. tungsten) over the source-drain regions and the polysilicon gate.In an alternative embodiment of this process, after forming the highly doped polysilicon gate using a mask, lightly doped source-drain regions which are self-aligned and in registry with the gate are formed by ion implantation.

Abstract: Disclosed is a process for forming self-aligned polysilicon gates and interconnecting conductors having a single conductivity and single impurity type in CMOS integrated circuits. After forming a polysilicon layer over the gate oxide, the polysilicon is doped with n-type impurities. Next, the polysilicon is covered with a relatively thick oxide serving as an implantation mask and then patterned into gates and conductors. Finally, by using ion implantation sources and drains for the p-FET and n-FET are formed in a self-aligned relationship with the corresponding gates.

Abstract: A method of forming planar silicon structures having recessed dielectric isolation oxide regions in which the bird's beak and bird's head associated with the silicon dioxide-silicon nitride dual mask are eliminated. After forming the pad oxide-nitride dual mask, photoresist is used for patterning the active device area and creating a photoresist overhang. Arsenic ions are then implanted and diffused in the isolation regions. Then, using a low (700.degree.-800.degree. C.) temperature wet oxidation, the doped silicon is fully converted to silicon dioxide forming a standard planar structure.A true coplanar structure is obtained by continuing the process by etching the grown oxide and causing the nitride mask to overhang the pad oxide. Then, arsenic ions of a lower energy than before are implanted and diffused in the field regions, which regions are subsequently oxidized at the same low temperature as before forming the final planar structure having completely inset oxide regions.