Patents by Inventor Samuele Raffaelli

Samuele Raffaelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit for performing a multiply-and-accumulate operation
    Patent number: 10437558
    Abstract: A circuit includes a multiplier, an adder, a first result register and a second result register coupled to outputs of the multiplier and the adder, respectively. The circuit further includes: a first selection unit configured to selectively provide, to the multiplier and in response to a first control signal, a first value from a first plurality of values; and a second selection unit configured to selectively provide, to the multiplier and in response to a second control signal, a second value from a second plurality of values. The circuit also includes: a third selection unit configured to selectively provide, to the adder and in response to a third control signal, a third value from a third plurality of values; and a fourth selection unit configured to selectively provide, to the adder and in response to a fourth control signal, a fourth value from a fourth plurality of values.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: October 8, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: David Vincenzoni, Samuele Raffaelli
  • CIRCUIT FOR PERFORMING A MULTIPLY-AND-ACCUMULATE OPERATION
    Publication number: 20190012143
    Abstract: A circuit includes a multiplier, an adder, a first result register and a second result register coupled to outputs of the multiplier and the adder, respectively. The circuit further includes: a first selection unit configured to selectively provide, to the multiplier and in response to a first control signal, a first value from a first plurality of values; and a second selection unit configured to selectively provide, to the multiplier and in response to a second control signal, a second value from a second plurality of values. The circuit also includes: a third selection unit configured to selectively provide, to the adder and in response to a third control signal, a third value from a third plurality of values; and a fourth selection unit configured to selectively provide, to the adder and in response to a fourth control signal, a fourth value from a fourth plurality of values.
    Type: Application
    Filed: August 28, 2018
    Publication date: January 10, 2019
    Inventors: David Vincenzoni, Samuele Raffaelli
  • Circuit for performing a multiply-and-accumulate operation
    Patent number: 10089078
    Abstract: A circuit includes a multiplier, an adder, a first result register and a second result register coupled to outputs of the multiplier and the adder, respectively. The circuit further includes: a first selection unit configured to selectively provide, to the multiplier and in response to a first control signal, a first value from a first plurality of values; and a second selection unit configured to selectively provide, to the multiplier and in response to a second control signal, a second value from a second plurality of values. The circuit also includes: a third selection unit configured to selectively provide, to the adder and in response to a third control signal, a third value from a third plurality of values; and a fourth selection unit configured to selectively provide, to the adder and in response to a fourth control signal, a fourth value from a fourth plurality of values.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: October 2, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: David Vincenzoni, Samuele Raffaelli
  • Circuit for Performing a Multiply-and-Accumulate Operation
    Publication number: 20180088908
    Abstract: A circuit includes a multiplier, an adder, a first result register and a second result register coupled to outputs of the multiplier and the adder, respectively. The circuit further includes: a first selection unit configured to selectively provide, to the multiplier and in response to a first control signal, a first value from a first plurality of values; and a second selection unit configured to selectively provide, to the multiplier and in response to a second control signal, a second value from a second plurality of values. The circuit also includes: a third selection unit configured to selectively provide, to the adder and in response to a third control signal, a third value from a third plurality of values; and a fourth selection unit configured to selectively provide, to the adder and in response to a fourth control signal, a fourth value from a fourth plurality of values.
    Type: Application
    Filed: September 23, 2016
    Publication date: March 29, 2018
    Inventors: David Vincenzoni, Samuele Raffaelli