Abstract: A circuit portion comprises a DCDC converter arranged to provide current from an output of the converter to one of a plurality of loads at a time. The plurality of loads includes a low priority load and a primary load. In response to the controller detecting, while the DCDC converter is providing current to the low priority load, that the voltage across the primary load is below a first threshold, channel logic circuitry is configured to stop providing current from the output of the converter to the low priority load and to provide current from the output of the converter to the primary load. A voltage regulator provides current to the low priority load when the voltage across the low priority load is below a second threshold.

Abstract: This document describes a solution for low-power voltage regulation. According to an aspect, there is provided an apparatus comprising: a supply voltage regulator circuit configured to regulate a power supply voltage of a circuit; a comparator circuit coupled to the power supply voltage and configured to sample the power supply voltage, to compare the sampled power supply voltage with a reference voltage and, if the sampled power supply voltage is below the reference voltage, to enable the supply voltage regulator circuit to charge the power supply voltage, wherein the comparator is switched on and off in response to a clock signal; and a clock signal generator circuit configured to generate the clock signal.

Abstract: A circuit portion comprises a DCDC converter that provides current from an output to a plurality of loads. Channel logic circuitry is configured to provide current from the output of the converter to each load according to a cyclical sequence, wherein each cycle has a duration that is divided equally into a plurality of time slots. The channel logic circuitry is configured to provide current to each load for one or more discrete time slots. The number of time slots is greater than the number of loads so that at least two output loads receive current for different numbers of time slots in a cycle.

Abstract: A circuit portion comprises a DCDC converter that is configured to charge and discharge an inductor according to a duty cycle to provide current to an output load. A duty module is configured to determine the duty cycle such that the DCDC converter will output a target current. A duty limiter module is configured to cause the inductor to discharge early if the determined duty cycle exceeds a threshold.

Abstract: A circuit portion comprises a DCDC converter that provides current to one of a plurality of loads at a time. A controller detects when a voltage across an under-supplied load of the plurality of loads is below a first threshold. Channel logic circuitry provides current from the converter to the under-supplied load in response to the controller detecting that the voltage is below the first threshold. A voltage regulator provides current to the under-supplied load when the voltage is below a second threshold.

Abstract: A power supply circuit portion for supplying power comprises a first power rail, a second power rail, first and second output terminals, an energy storage device connected in parallel with the first and second output terminals; and first and second switching portions. The power supply circuit portion has a first mode in which power is supplied to the first and second output terminals by the first and second power rails, and a second mode in which the first switching portion is arranged such that power is not supplied to the first and second output terminals and the second switching portion is arranged to disconnect the energy storage device from the first power rail.

Abstract: This document describes a solution for low-power voltage regulation. According to an aspect, there is provided an apparatus comprising: a supply voltage regulator circuit configured to regulate a power supply voltage of a circuit; a comparator circuit coupled to the power supply voltage and configured to sample the power supply voltage, to compare the sampled power supply voltage with a reference voltage and, if the sampled power supply voltage is below the reference voltage, to enable the supply voltage regulator circuit to charge the power supply voltage, wherein the comparator is switched on and off in response to a clock signal; and a clock signal generator circuit configured to generate the clock signal.

Abstract: A circuit portion comprises a DCDC converter that provides current from an output to a plurality of loads. Channel logic circuitry is configured to provide current from the output of the converter to each load according to a cyclical sequence, wherein each cycle has a duration that is divided equally into a plurality of time slots. The channel logic circuitry is configured to provide current to each load for one or more discrete time slots. The number of time slots is greater than the number of loads so that at least two output loads receive current for different numbers of time slots in a cycle.

Abstract: A circuit portion comprises a DCDC converter that is configured to charge and discharge an inductor according to a duty cycle to provide current to an output load. A duty module is configured to determine the duty cycle such that the DCDC converter will output a target current. A duty limiter module is configured to cause the inductor to discharge early if the determined duty cycle exceeds a threshold.

Abstract: A power supply circuit portion for supplying power comprises a first power rail, a second power rail, first and second output terminals, an energy storage device connected in parallel with the first and second output terminals; and first and second switching portions. The power supply circuit portion has a first mode in which power is supplied to the first and second output terminals by the first and second power rails, and a second mode in which the first switching portion is arranged such that power is not supplied to the first and second output terminals and the second switching portion is arranged to disconnect the energy storage device from the first power rail.

Abstract: A low-dropout voltage regulator is arranged to convert an input voltage to an output voltage. The low-dropout voltage regulator comprises: an error amplifier circuit portion arranged to produce an error signal proportional to a difference between a sense voltage (Vsense) and a reference voltage (Vref), wherein the sense voltage is derived from the output voltage; a pass field-effect-transistor (MP) connected to the input voltage; and a rail-to-rail buffer circuit portion connected between the input voltage (VDD) and ground. The rail-to-rail buffer circuit portion comprises: a buffer input arranged to receive the error signal; a buffer output arranged to apply a buffer signal to the gate terminal of the pass field-effect-transistor, wherein the buffer signal is a buffered version of the error signal; and a resistive bypass arrangement (Rbypass) connected between the buffer input and the buffer output.

Abstract: A low-dropout voltage regulator is arranged to convert an input voltage to an output voltage. The low-dropout voltage regulator comprises: an error amplifier circuit portion arranged to produce an error signal proportional to a difference between a sense voltage (Vsense) and a reference voltage (Vref), wherein the sense voltage is derived from the output voltage; a pass field-effect-transistor (MP) connected to the input voltage; and a rail-to-rail buffer circuit portion connected between the input voltage (VDD) and ground. The rail-to-rail buffer circuit portion comprises: a buffer input arranged to receive the error signal; a buffer output arranged to apply a buffer signal to the gate terminal of the pass field-effect-transistor, wherein the buffer signal is a buffered version of the error signal; and a resistive bypass arrangement (Rbypass) connected between the buffer input and the buffer output.

Abstract: A low-dropout voltage regulator arranged to regulate an output voltage (VDD) comprising: a differential amplifier portion including a first amplifier input connected to a reference voltage (VREF), a second amplifier input, and a differential output which is determined by a difference between the reference voltage and a voltage on the second amplifier input; an output portion arranged to provide a regulator output voltage controlled by the differential output of the differential amplifier portion, wherein the second amplifier input is connected to or derived from the regulator output voltage; a first biasing portion arranged to provide a first bias current to the differential amplifier portion which depends on an external load current; and a second biasing portion comprising a DC-blocking capacitor (C0) connected to the output portion so as to provide a second bias current to the differential amplifier portion which depends on the rate of change of the output voltage.

Abstract: A voltage regulation circuit (2) comprises first (4) and second (6) voltage regulators each arranged to receive an input voltage (Vin) and a respective reference voltage; and first (18) and second (30) reference voltage sources arranged to provide the first and second reference voltages respectively. In a first mode of operation, the first regulator varies the regulated output voltage in response to a difference between the regulated output voltage (Vout) and the first reference voltage. In a second mode of operation, the second regulator varies the regulated output voltage in response to a difference between the regulated output voltage and the second reference voltage. The second voltage regulator is arranged to provide a greater maximum output current than the first voltage regulator. The circuit further comprises a switch portion (8) arranged to provide a third mode of operation in which the first regulator provides the regulated output voltage and the second regulator provides additional output current.

Abstract: A reference voltage circuit 2 comprises: a bandgap circuit portion comprising first and second reference transistors (Q1, Q2) and a current source arranged to drive the first and second reference transistor at different current densities, wherein the first and second reference transistors are connected to first and second nodes (N1, N2) respectively; an operational transconductance amplifier (M4, M5, M10, M11, M12) arranged to produce an output current that is proportional to a difference between a voltage at the first node and a voltage at the second node; an output current mirror circuit portion (M3) arranged to generate a mirror current that is a scaled version of the output current and drive said mirror current through a load (R3) so as to produce a reference voltage (Vref); and a reference monitoring circuit portion (6) arranged to monitor the operational transconductance amplifier and generate a flag (Vready) if a current flowing through the operational transconductance amplifier exceeds a threshold.

Abstract: A reference voltage circuit 2 comprises: a bandgap circuit portion comprising first and second reference transistors (Q1, Q2) and a current source arranged to drive the first and second reference transistor at different current densities, wherein the first and second reference transistors are connected to first and second nodes (N1, N2) respectively; an operational transconductance amplifier (M4, M5, M10, M11, M12) arranged to produce an output current that is proportional to a difference between a voltage at the first node and a voltage at the second node; an output current mirror circuit portion (M3) arranged to generate a mirror current that is a scaled version of the output current and drive said mirror current through a load (R3) so as to produce a reference voltage (Vref); and a reference monitoring circuit portion (6) arranged to monitor the operational transconductance amplifier and generate a flag (Vready) if a current flowing through the operational transconductance amplifier exceeds a threshold.

Abstract: A voltage regulation circuit (2) comprises first (4) and second (6) voltage regulators each arranged to receive an input voltage (Vin) and a respective reference voltage; and first (18) and second (30) reference voltage sources arranged to provide the first and second reference voltages respectively. In a first mode of operation, the first regulator varies the regulated output voltage in response to a difference between the regulated output voltage (Vout) and the first reference voltage. In a second mode of operation, the second regulator varies the regulated output voltage in response to a difference between the regulated output voltage and the second reference voltage. The second voltage regulator is arranged to provide a greater maximum output current than the first voltage regulator. The circuit further comprises a switch portion (8) arranged to provide a third mode of operation in which the first regulator provides the regulated output voltage and the second regulator provides additional output current.