Abstract: A method and apparatus for conducting a transition test of a source synchronous interface is disclosed. A system includes a source synchronous transmitter and source synchronous receiver. The source synchronous transmitter includes a first scannable flop having an output coupled to a data input of a second scannable flop in the source synchronous receiver. During a transition test, the source synchronous transmitter is configured to transmit data from the first scannable flop to the second scannable flop, along with a clock signal at an operational clock speed. The first scannable flop is coupled to feedback circuitry configured to cause transitions of the transmitted data. The second scannable flop may capture the transmitted data. The captured data may be subsequently used to determine if the desired transitions were detected by the second scannable flop.

Abstract: An apparatus and method for controlling a test controller is disclosed. An apparatus includes test controllers of a first type configured to operate according to a first protocol and test controllers of a second type configured to operate according to a second protocol. A test controller of the second type may be associated with one of the test controllers of the first type, with the former controlling the latter. The test controllers of the second type may each control associated ones of the test controllers of the second type in parallel and independently of one another.

Abstract: A method and apparatus for detecting clock glitches during at-speed testing of integrated circuits is disclosed. In one embodiment, an integrated circuit includes a scan chain having a number of scan elements coupled in a series configuration. Each of the scan elements is coupled to receive a clock signal that may be cycled during a test operation. A subset of the scan elements are arranged to form, along with other components, a counter. Test stimulus data shifted into the scan chain to perform a test may include an initial count value that is shifted into the scan elements of the counter. When the test is performed, the count value is updated responsive to cycling of the clock signal. The updated count value is shifted from the counter along with other test result data, and may be used to determine if the number of clock cycles received during the test.

Abstract: A method and apparatus for conducting a transition test of a source synchronous interface is disclosed. A system includes a source synchronous transmitter and source synchronous receiver. The source synchronous transmitter includes a first scannable flop having an output coupled to a data input of a second scannable flop in the source synchronous receiver. During a transition test, the source synchronous transmitter is configured to transmit data from the first scannable flop to the second scannable flop, along with a clock signal at an operational clock speed. The first scannable flop is coupled to feedback circuitry configured to cause transitions of the transmitted data. The second scannable flop may capture the transmitted data. The captured data may be subsequently used to determine if the desired transitions were detected by the second scannable flop.

Abstract: A method and apparatus for detecting clock glitches during at-speed testing of integrated circuits is disclosed. In one embodiment, an integrated circuit includes a scan chain having a number of scan elements coupled in a series configuration. Each of the scan elements is coupled to receive a clock signal that may be cycled during a test operation. A subset of the scan elements are arranged to form, along with other components, a counter. Test stimulus data shifted into the scan chain to perform a test may include an initial count value that is shifted into the scan elements of the counter. When the test is performed, the count value is updated responsive to cycling of the clock signal. The updated count value is shifted from the counter along with other test result data, and may be used to determine if the number of clock cycles received during the test.

Abstract: A multi-processor chip has several processor cores that are simultaneously tested in parallel. The processor cores each have identical scan chains that produce identical test results absent defects. Expected test data is scanned from an external tester onto the chip and replicated to each processor core's scan chain. The expected test data is compared to scan chain outputs at each processor core. Any mismatches set a test-fail bit for that processor core. Each processor core has repairable scan chains and a separate critical scan chain. Failures in the critical scan chain in any processor core cause the whole chip to fail. Processor cores are disabled that have failures in their repairable scan chains, allowing the chip to be repairable by using the remaining processor cores. Critical scan chains include logic that drives to other blocks on the chip, while repairable scan chains have logic embedded deep within a processor core.