Patents by Inventor San-An Lin

San-An Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8532948
    Abstract: A contactless sensing device comprises a magnetic stripe fixed on a tested object, a detector and a processor. The magnetic stripe has arranged plurality of N-pole and S-pole blocks. The detector includes a fixed magnetic layer with fixed magnetic direction, a free magnetic layer with changeable magnetic direction influenced by external magnetic field, and an insulating layer separated the fixed magnetic layer from the free magnetic layer. While the object is moving to make the magnetic stripe pass through the detector, the magnetic direction of the free magnetic layer is influenced by the N-pole and S-pole blocks, such that the magnetic direction of the free magnetic layer is parallel or anti-parallel to the fixed magnetic layer. The induced change of the magnetoresistance further result in the obvious change of the output signal to the processor, and then the information of the object is sensed and calculated from the processor.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: September 10, 2013
    Inventors: Geeng-Jen Sheu, San-Lin Young, Heng-Hui Chen, Shih-Hung Yeh
  • Patent number: 8518743
    Abstract: A die structure and a die connecting method using the same are provided. The die structure includes a die and a bump structure. The bump structure includes a body and a solder layer. The body is disposed on the die. The solder layer is disposed on the body. The method includes providing a die structure mentioned above, providing a circuit board mentioned above, and soldering the solder layer of the die structure with the tine layer on the copper block of the circuit board. In different embodiments, a tin layer is omitted from the circuit board, wherein the solder layer of the die structure is directly soldered onto the surface of the copper block.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: August 27, 2013
    Assignee: Raydium Semiconductor Corporation
    Inventors: Chia-Hung Hsu, Ching-San Lin, Chin-Yung Chen
  • Patent number: 8421671
    Abstract: An alternate radio transmitter includes a processor, a modulator, a PLL unit and a radio transmission unit. The processor provides a digital signal. The modulator modulates the digital signal, thus providing at least two modulated signals. The PLL unit mixes the modulated signals, thus providing an output signal. The radio transmission unit transmits the output signal.
    Type: Grant
    Filed: December 4, 2010
    Date of Patent: April 16, 2013
    Assignee: Chung-San Institute of Science and Technology, Armaments, Bureau, Ministry of National Defense
    Inventors: Yu-Cheng Chang, Yu-San Lin, Feng-Yu Chang
  • Patent number: 8319354
    Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: November 27, 2012
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Hsin-Jung Lo, Chien-Kang Chou, Chiu-Ming Chou, Ching-San Lin
  • Publication number: 20120248309
    Abstract: A specimen grid holder includes a base and two holding members disposed thereon. Each holding member has at least one inserting portion and at least one holding portion formed adjacently. The specimen grid can be inserted into the inserting portion and moved to the holding portion for securement. The two holding members can be used to secure specimens at different orientations for analyses.
    Type: Application
    Filed: September 7, 2011
    Publication date: October 4, 2012
    Applicant: INOTERA MEMORIES, INC.
    Inventors: SAN LIN LIEW, YU-TZU HUANG
  • Patent number: 8242601
    Abstract: The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: August 14, 2012
    Assignee: Megica Corporation
    Inventors: Chiu-Ming Chou, Chien-Kang Chou, Ching-San Lin, Mou-Shiung Lin
  • Publication number: 20120092216
    Abstract: An alternate radio transmitter includes a processor, a modulator, a PLL unit and a radio transmission unit. The processor provides a digital signal. The modulator modulates the digital signal, thus providing at least two modulated signals. The PLL unit mixes the modulated signals, thus providing an output signal. The radio transmission unit transmits the output signal.
    Type: Application
    Filed: December 4, 2010
    Publication date: April 19, 2012
    Applicant: Chung-Shan Institute of Science and Technology, Armaments, Bureau, Ministry of National Defense
    Inventors: Yu-Cheng Chang, Yu-San Lin, Feng-Yu Chang
  • Publication number: 20120050013
    Abstract: Disclosed is an economic method for operating an active tag. The active tag includes a pulse module, a power supply module and a signal module. The economic method includes the steps of providing a signal to the pulse module so that the pulse module identifies the signal, and providing a trigger signal to the power supply module from the pulse module to instruct the power supply module to energize the signal module so that the active tag is turned to an active state from sleep.
    Type: Application
    Filed: December 4, 2010
    Publication date: March 1, 2012
    Applicant: Chung-Shan Institute of Science and Technology, Armaments, Bureau, Ministry of National Defense
    Inventors: Yu-Cheng Chang, Yu-San Lin, Feng-Yu Chang
  • Publication number: 20120018880
    Abstract: A semiconductor structure and a manufacture method thereof are disclosed. The semiconductor structure includes a semiconductor wafer having a plurality of semiconductor device dies, wherein each of the semiconductor device dies includes a die body, a metal wiring layer, a bump, and a metal layer. The metal wiring layer is formed on the die body while the bump is formed on the metal wiring layer during the semiconductor front-end-of-line (FEOL) process and protrudes from the die body. The metal layer is disposed on one side of the bump opposite to the metal wiring layer, wherein the activity of the metal layer is smaller than the activity of the bump. In this way, the semiconductor structure of the present invention is easy to be manufactured and the manufacture cost is also reduced.
    Type: Application
    Filed: June 29, 2011
    Publication date: January 26, 2012
    Inventors: Kun-Tai Wu, Ching-San Lin, Owen Wang
  • Patent number: 8093877
    Abstract: A transient voltage compensation apparatus and a power supply using the same are provided. The power supply mainly uses a compensation circuit coupled between an input terminal and an output terminal of a power converter. When a load of the power supply is switched in a very short time, a power coupled to the compensation circuit is retrieved to compensate the output of the power supply, such that the output voltage is kept steady, and the transient response of the power supply is increased.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: January 10, 2012
    Assignee: ASUSTeK Computer Inc.
    Inventors: Yun-Jiun You, Hsiang-Jui Hung, Chun-San Lin, Han-Hsun Chen, Sun-Chen Yang
  • Publication number: 20120003817
    Abstract: An integrated circuit wafer dicing method is provided. The method includes forming a plurality of integrated circuits and a plurality of test-keys on a wafer substrate, wherein the plurality of test-keys are disposed between the adjacent integrated circuits; forming a patterned protective film on the wafer to cover the plurality of integrated circuits and expose the plurality of test-keys; etching the plurality of test-keys by using the patterned protective film as a mask; and dicing an area between the plurality of integrated circuits to form a plurality of discrete integrated circuit dies.
    Type: Application
    Filed: June 24, 2011
    Publication date: January 5, 2012
    Inventors: Ching-San Lin, Kun-Tai Wu, Chih-Chao Wang
  • Publication number: 20110266669
    Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer.
    Type: Application
    Filed: July 12, 2011
    Publication date: November 3, 2011
    Applicant: MEGICA CORPORATION
    Inventors: Chiu-Ming Chou, Chien-Kang Chou, Ching-San Lin, Mou-Shiung Lin, Hsin-Jung Lo
  • Publication number: 20110254153
    Abstract: A die structure and a die connecting method using the same are provided. The die structure includes a die and a bump structure. The bump structure includes a body and a solder layer. The body is disposed on the die. The solder layer is disposed on the body. The method includes providing a die structure mentioned above, providing a circuit board mentioned above, and soldering the solder layer of the die structure with the tine layer on the copper block of the circuit board. In different embodiments, a tin layer is omitted from the circuit board, wherein the solder layer of the die structure is directly soldered onto the surface of the copper block.
    Type: Application
    Filed: April 19, 2011
    Publication date: October 20, 2011
    Inventors: Chia-Hung Hsu, Ching-San Lin, Chin-Yung Chen
  • Publication number: 20110254152
    Abstract: An IC chip and an IC chip manufacturing method thereof are provided. The IC chip has a chip body and at least one bump. The chip body has at least one conducting area on its surface. The bump is formed on the conducting area of the chip body. The bump includes a plurality of protrusions and at least one conducting material. The protrusions protrude out of the conducting area and are spaced apart from each other. The conducting material covers the protrusions and electrically connects the conducting area. The method includes: (A) providing a chip body having a conducting area on its surface; (B) forming a plurality of protrusions on the chip body, wherein the protrusions protrude out of the conducting area and are spaced apart from each other; and (C) forming at least one conducting material, wherein the conducting material covers the protrusions and electrically connects the conducting area.
    Type: Application
    Filed: April 19, 2011
    Publication date: October 20, 2011
    Inventor: Ching-San Lin
  • Patent number: 8004092
    Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: August 23, 2011
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Hsin-Jung Lo, Chien-Kang Chou, Chiu-Ming Chou, Ching-San Lin
  • Publication number: 20110196635
    Abstract: A contactless sensing device comprises a magnetic stripe fixed on a tested object, a detector and a processor. The magnetic stripe has arranged plurality of N-pole and S-pole blocks. The detector includes a fixed magnetic layer with fixed magnetic direction, a free magnetic layer with changeable magnetic direction influenced by external magnetic field, and an insulating layer separated the fixed magnetic layer from the free magnetic layer. While the object is moving to make the magnetic stripe pass through the detector, the magnetic direction of the free magnetic layer is influenced by the N-pole and S-pole blocks, such that the magnetic direction of the free magnetic layer is parallel or anti-parallel to the fixed magnetic layer. The induced change of the magnetoresistance further result in the obvious change of the output signal to the processor, and then the information of the object is sensed and calculated from the processor.
    Type: Application
    Filed: January 31, 2011
    Publication date: August 11, 2011
    Inventors: GEENG-JEN SHEU, San-Lin Young, Heng-Hui Chen, Shih-Hung Yeh
  • Publication number: 20110080799
    Abstract: A fluid processing system includes a first tube having a conductor disposed in the first tube, and a flow path disposed in the fluid processing system; the conductor is capable of being connected to a power supply unit such that when the power supply unit is turned on, the conductor is magnetized, and the fluid is refined by magnetic lines of force. An auger is disposed on an outer sidewall of the conductor to form a screw.
    Type: Application
    Filed: July 3, 2010
    Publication date: April 7, 2011
    Inventor: Cheng San Lin
  • Publication number: 20100171474
    Abstract: A transient voltage compensation apparatus and a power supply using the same are provided. The power supply mainly uses a compensation circuit coupled between an input terminal and an output terminal of a power converter. When a load of the power supply is switched in a very short time, a power coupled to the compensation circuit is retrieved to compensate the output of the power supply, such that the output voltage is kept steady, and the transient response of the power supply is increased.
    Type: Application
    Filed: March 17, 2010
    Publication date: July 8, 2010
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Yun-Jiun You, Hsiang-Jui Hung, Chun-San Lin, Han-Hsun Chen, Sun-Chen Yang
  • Patent number: 7714559
    Abstract: A transient voltage compensation apparatus and a power supply using the same are provided. The power supply mainly uses an energy transferring circuit coupled between an input terminal and an output terminal of a power converter. When a load of the power supply is switched in a very short time, a power coupled to the energy transferring circuit is retrieved to compensate the output of the power supply, such that the output voltage is kept steady, and the transient response of the power supply is increased.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: May 11, 2010
    Assignee: ASUSTeK Computer Inc.
    Inventors: Yun-Jiun You, Hsiang-Jui Hung, Chun-San Lin, Han-Hsun Chen, Sun-Chen Yang
  • Publication number: 20090218687
    Abstract: The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.
    Type: Application
    Filed: May 13, 2009
    Publication date: September 3, 2009
    Applicant: MEGICA CORPORATION
    Inventors: Chiu-Ming Chou, Chien-Kang Chou, Ching-San Lin, Mou-Shiung Lin