Patents by Inventor San-Jin Lee

San-Jin Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240112002
    Abstract: Disclosed is an interface system including a first neuron cluster that outputs a first neuron signal including a first neuron request and first neuron data by performing a first arithmetic operation, and a first interface circuit that stores the first neuron data and outputs a first response, in response to the first neuron request. The first neuron cluster outputs a second neuron signal including a second neuron request and second neuron data by performing a second arithmetic operation, in response to the first response. Before the first data is transmitted to a second neuron cluster different from the first neuron cluster, the first interface circuit outputs the first response in response to a fact that the first neuron data is stored.
    Type: Application
    Filed: June 29, 2023
    Publication date: April 4, 2024
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sung Eun KIM, Tae Wook KANG, Hyuk KIM, Young Hwan BAE, Kyung Jin BYUN, Kwang IL OH, Jae-Jin LEE, In San JEON
  • Patent number: 8711388
    Abstract: A controlling method of an image forming apparatus includes receiving a wake up command for the image forming apparatus in a power save mode; confirming prestored authority of a user to use a plurality of operations of the image forming apparatus; and selectively performing warming up for at least one operation of the image forming apparatus according to the authority of the user.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: San-jin Lee, Gun-il Lee, Seung-kyoon Shin
  • Publication number: 20100013514
    Abstract: A test device and a semiconductor integrated circuit are provided. The test device may include a first test region and a second test region defined on a semiconductor substrate. The first test region may include a first test element and the second region may include a second test element. The first test element may include a pair of first secondary test regions in the semiconductor substrate extending in a first direction. The second test element may include structures corresponding to the first test element except the second test element does not include structures corresponding to the pair of first secondary test regions.
    Type: Application
    Filed: July 15, 2009
    Publication date: January 21, 2010
    Inventors: San-Jin Lee, Gin-Kyu Lee