Abstract: The present invention provides a silicon capacitor structure, including a substrate, an interlayer dielectric (ILD) layer on the substrate, a capacitor recess extending from a surface of the ILD layer into the substrate, a capacitor in the capacitor recess, wherein the capacitor includes a bottom electrode on a surface of the capacitor recess, a capacitive dielectric layer on a surface of the bottom electrode, and a top electrode on a surface of the capacitive dielectric layer and filling up the capacitor recess.

Abstract: A semiconductor structure including a substrate, a first isolation structure and a capacitor is provided. The substrate includes a capacitor region. The first isolation structure is disposed in the substrate in the capacitor region. The capacitor is located in the capacitor region. The capacitor includes the substrate in the capacitor region, an electrode layer and a first dielectric layer. The electrode layer is disposed in the substrate in the capacitor region. The first dielectric layer is disposed between the electrode layer and the substrate and between the electrode layer and the first isolation structure. The first dielectric layer is in direct contact with the first isolation structure.

Abstract: Provided is a dynamic random access memory (DRAM) including a substrate, a plurality of word-line sets, a plurality of bit-line structures, a plurality of capacitors, a plurality of capacitor contacts, and a plurality of air gaps. The substrate has a plurality of active areas. The word-line sets extend along a Y direction and disposed in the substrate. The bit-line structures extend along a X direction, disposed on the substrate, and across the word-line sets. The capacitors are respectively disposed at two terminals of the active areas. The capacitor contacts are respectively disposed between the capacitors and the active regions. The air gaps are disposed in a plurality of spaces enclosed by the bit-line structures and the capacitor contacts. A method of forming a DRAM is also provided.

Abstract: Provided is a dynamic random access memory (DRAM) including a substrate, a plurality of word-line sets, a plurality of bit-line structures, a plurality of capacitors, a plurality of capacitor contacts, and a plurality of air gaps. The substrate has a plurality of active areas. The word-line sets extend along a Y direction and disposed in the substrate. The bit-line structures extend along a X direction, disposed on the substrate, and across the word-line sets. The capacitors are respectively disposed at two terminals of the active areas. The capacitor contacts are respectively disposed between the capacitors and the active regions. The air gaps are disposed in a plurality of spaces enclosed by the bit-line structures and the capacitor contacts. A method of forming a DRAM is also provided.

Abstract: A method of fabricating a metal-oxide-semiconductor (MOS) transistor is provided. First, a patterned hard mask layer with an opening therein is formed over the substrate. A spacer is formed on the sidewall of the patterned hard mask layer in the opening. An isotropic etching process is performed on the substrate to form a recess in the substrate. An ion implant process is performed on the substrate in the lower portion of the recess using oxidation-restrained ions. The spacer is removed. Then, a thermal process is performed to form a gate oxide layer on the surface of the substrate within the recess such that the gate oxide layer in the upper portion of the recess is thicker than that in the lower portion of the recess.

Abstract: A semiconductor device comprising a substrate, a gate structure disposed on the substrate, and a source/drain area disposed in the substrate is provided. The source/drain area comprises a silicon layer and a glass layer below the silicon layer, so as to define a shallow junction depth to avoid the possible short channel effect.

Abstract: A semiconductor device with a recessed channel and a method of fabricating the same are provided. The semiconductor device comprises a substrate, a gate, a source, a drain, and a reverse spacer. The substrate comprises a recessed trench. The gate is formed above the recessed trench and extends above the substrate. The gate further comprises a polysilicon layer and a conductive layer; wherein the polysilicon layer is formed inside the recessed trench of the substrate, and the conductive layer is formed above the polysilicon layer and extends above the substrate. Moreover, the width of the conductive layer increases gradually bottom-up. The source and the drain are formed respectively at two sides of the gate. The reverse spacer is formed above the polysilicon layer and against the sidewall of the conductive layer.

Abstract: A method of fabricating a metal-oxide-semiconductor (MOS) transistor is provided. First, a patterned hard mask layer with an opening therein is formed over the substrate. A spacer is formed on the sidewall of the patterned hard mask layer in the opening. An isotropic etching process is performed on the substrate to form a recess in the substrate. An ion implant process is performed on the substrate in the lower portion of the recess using oxidation-restrained ions. The spacer is removed. Then, a thermal process is performed to form a gate oxide layer on the surface of the substrate within the recess such that the gate oxide layer in the upper portion of the recess is thicker than that in the lower portion of the recess.

Abstract: A semiconductor device with a recessed channel and a method of fabricating the same are provided. The semiconductor device comprises a substrate, a gate, a source, a drain, and a reverse spacer. The substrate comprises a recessed trench. The gate is formed above the recessed trench and extends above the substrate. The gate further comprises a polysilicon layer and a conductive layer; wherein the polysilicon layer is formed inside the recessed trench of the substrate, and the conductive layer is formed above the polysilicon layer and extends above the substrate. Moreover, the width of the conductive layer increases gradually bottom-up. The source and the drain are formed respectively at two sides of the gate. The reverse spacer is formed above the polysilicon layer and against the sidewall of the conductive layer.

Abstract: The invention provides an isolation technique using fewer process steps and a double charged implantation step (141) for defining a well region (139) of a CMOS integrated circuit device. The invention provides steps of providing a semiconductor substrate comprising an multiple layer of films (105, 107, 109). These films include an oxide layer (105) overlying the substrate, a polysilicon layer (107) overlying the oxide layer, and a nitride layer (109) overlying the polysilicon layer. The invention also uses a step of removing a first portion of the nitride layer and a first portion of the polysilicon layer defined underlying the first portion of the nitride layer and removing a second portion of the nitride layer and a second portion of the polysilicon layer defined underlying the second portion of the nitride layer. This sequence of steps provides a partially completed semiconductor structure that defines isolation regions before forming well regions for active devices.

Abstract: The present invention is related to a process for fabricating a MOS device having a short channel. The process according to the present invention includes the steps of (a) providing a semiconductor substrate and forming a gate structure on the semiconductor substrate; (b) implanting impurities of a first charge type to the semiconductor substrate with the gate structure serving as a mask to form a first source/drain region having a predetermined impurity concentration; (c) pocket-implanting impurities of a second charge type to the resulting semiconductor substrate with the gate structure serving as a mask to form a second source/drain region having a predetermined impurity concentration; and (d) forming a gate side wall on a flank of the gate structure, and implanting impurities of the first charge type to the resulting semiconductor substrate with the gate structure and the gate side wall serving as a mask to form a third source/drain region having a predetermined impurity concentration.

Abstract: A method for forming retrograde semiconductor substrate channel impurities profile of a semiconductor device by using phosphorus ions implantation, includes the steps of forming a sacrificial oxide layer on a semiconductor substrate, ion-implanting boron ions to adjust threshold voltage of the device, removing the sacrificial oxide layer, forming a gate oxide layer on the semiconductor substrate, depositing a gate polysilicon layer on the gate oxide layer, forming a gate by etching the gate polysilicon layer, ion-implanting firstly by implanting phosphorus ions to form lightly doped drain regions, and ion-implanting secondly by implanting phosphorus ions into the semiconductor substrate channel to form retrograde channel impurities profile as well as to achieve proper threshold voltage.