Patents by Inventor San Yu

San Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10712781
    Abstract: A casing assembly of an electronic device is provided. The casing assembly of the electronic device is configured to connect a connecting assembly. The connecting assembly comprises a metal casing; and an injection-molded frame. The injection-molded frame includes a first surface and a second surface, the first surface is fixed to the metal casing, and the second surface is configured with a plurality of connecting structures. The connecting structures are fixed to the connecting assembly, and the connecting assembly is assembled to the metal casing via the connecting structures.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: July 14, 2020
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: San-Feng Lin, Yen-Yu Chen
  • Publication number: 20190337273
    Abstract: A transparent stack structure includes a substrate and a hard coating layer stacked on the substrate. Compressive modulus and elastic restoration of the hard coating layer and the substrate satisfy Formula 1. Mechanical strength may be obtained from the substrate, and flexible and elastic properties may be enhanced by the hard coating layer so that cracks may be prevented when being folded or bent.
    Type: Application
    Filed: July 18, 2019
    Publication date: November 7, 2019
    Inventors: Myung Young AN, Sung Woo YU, Geo San LIM
  • Patent number: 10452113
    Abstract: A programmable-threshold power supply selector has two power-supply inputs VDD1 and VDD2. The higher of these two voltages is pre-selected as a common supply that powers all transistors and circuitry in the programmable-threshold power supply selector, including substrates under transistors. An open-loop decision circuit is very stable since it uses no feedback. A tunable voltage divider divides VDD1 by a programmable divisor. The divided VDD1 is compared to a reference voltage to generate switch-control signals. The switch-control signals drive the gates of p-channel switch transistors that connect either VDD1 or VDD2 to an output supply voltage. The different programmable divisor values effectively cause VDD1 to be compared to a programmable threshold voltage VTH. The switch transistors switch the output supply voltage to VDD2 only when VDD1 falls below VTH. The output supply voltage remains at VDD1 even when VDD1 falls below VDD2, eliminating unnecessary power switching.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: October 22, 2019
    Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
    Inventors: Chung Fai Au Yeung, Chi Hong Chan, Hok San Yu
  • Patent number: 10418978
    Abstract: An integrator in a duty-cycle adjustment circuit has an adjustable charging current provided by a switched current-source array in response to configuration signals from the calibration logic. The integrator's ramp voltage is compared to a threshold voltage by a comparator to generate an output clock. A tunable voltage reference generates a reference voltage that can be tuned by configuration signals from the calibration logic. The reference voltage is divided by a tunable voltage divider, which selects different fractions of the reference voltage for use as the threshold voltage. During calibration, calibration logic repeatedly raises the reference voltage or reduces the charging current from the switched current-source array until a peak voltage of the ramp voltage equals the reference voltage, when a zero duty onset detector detects that the output clock has stopped pulsing. The configuration signals at the zero duty onset condition are stored and used for normal operation.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: September 17, 2019
    Assignee: Hong Kong Applied Science and Technology Research Institute Company, Limited
    Inventors: Chung Fai Au Yeung, Gordon Chung, Hok San Yu
  • Publication number: 20190260031
    Abstract: A includes a cathode active material including a lithium transition metal oxide, wherein the lithium transition metal oxide includes nickel and a non-nickel transition metal, and an amount of the nickel in the lithium transition metal oxide is about 50 mole percent or greater with respect to a total number of moles of transition metals in the lithium transition metal oxide, a conducting agent including a linear carbonaceous conducting agent, and a binder, wherein the binder includes a first fluorinated binder not including a polar functional group, a second fluorinated binder including a polar functional group, a first non-fluorinated binder including a cyano group, and a second non-fluorinated binder including a cyanoalkyl group.
    Type: Application
    Filed: October 22, 2018
    Publication date: August 22, 2019
    Inventors: Youngsoo KIM, Byongyong YU, San MOON, Younggyoon RYU, Jinhwan PARK, Jaegu YOON, Byungjin CHOI
  • Publication number: 20190155354
    Abstract: A programmable-threshold power supply selector has two power-supply inputs VDD1 and VDD2. The higher of these two voltages is pre-selected as a common supply that powers all transistors and circuitry in the programmable-threshold power supply selector, including substrates under transistors. An open-loop decision circuit is very stable since it uses no feedback. A tunable voltage divider divides VDD1 by a programmable divisor. The divided VDD1 is compared to a reference voltage to generate switch-control signals. The switch-control signals drive the gates of p-channel switch transistors that connect either VDD1 or VDD2 to an output supply voltage. The different programmable divisor values effectively cause VDD1 to be compared to a programmable threshold voltage VTH. The switch transistors switch the output supply voltage to VDD2 only when VDD1 falls below VTH. The output supply voltage remains at VDD1 even when VDD1 falls below VDD2, eliminating unnecessary power switching.
    Type: Application
    Filed: November 20, 2017
    Publication date: May 23, 2019
    Inventors: Chung Fai AU YEUNG, Chi Hong CHAN, Hok San YU
  • Patent number: 9853177
    Abstract: A photovoltaic device includes a substrate, a transparent conductive oxide, an n-type window layer, a p-type absorber layer and an electron reflector layer. The electron reflector layer may include zinc telluride doped with copper telluride, zinc telluride alloyed with copper telluride, or a bilayer of multiple layers containing zinc, copper, cadmium and tellurium in various compositions. A process for manufacturing a photovoltaic device includes forming a layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process includes forming an electron reflector layer over a p-type absorber layer.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: December 26, 2017
    Assignee: First Solar, Inc.
    Inventors: San Yu, Veluchamy Palaniappagounder, Pratima Addepalli, Imran Khan
  • Patent number: 9450115
    Abstract: A method to improve CdTe-based photovoltaic device efficiency is disclosed, the method including steps for removing surface contaminants from a semiconductor absorber layer prior to the deposition or formation of a back contact layer on the semiconductor absorber layer, the surface contaminants removed using at least one of a dry etching process and a wet etching process.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: September 20, 2016
    Assignee: First Solar, Inc.
    Inventors: Scott Christensen, Pawel Mrozek, Gang Xiong, San Yu
  • Patent number: 9406829
    Abstract: A method to improve operation of a CdTe-based photovoltaic device is disclosed, the method comprising the steps of depositing a semiconductor absorber layer adjacent to a substrate, depositing a semiconductor buffer layer adjacent to the semiconductor layer, and annealing at least one of the semiconductor absorber layer and the semiconductor buffer layer with one of a laser and a flash lamp.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: August 2, 2016
    Assignee: First Solar, Inc.
    Inventors: Pratima Addepalli, Benyamin Buller, Markus Gloeckler, Akhlesh Gupta, David Hwang, Andrei Los, Rick Powell, Rui Shao, Gang Xiong, Ming Lun Yu, San Yu, Zhibo Zhao
  • Publication number: 20160126397
    Abstract: A photovoltaic device includes a substrate, a transparent conductive oxide, an n-type window layer, a p-type absorber layer and an electron reflector layer. The electron reflector layer may include zinc telluride doped with copper telluride, zinc telluride alloyed with copper telluride, or a bilayer of multiple layers containing zinc, copper, cadmium and tellurium in various compositions. A process for manufacturing a photovoltaic device includes forming a layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process includes forming an electron reflector layer over a p-type absorber layer.
    Type: Application
    Filed: January 11, 2016
    Publication date: May 5, 2016
    Applicant: First Solar, Inc.
    Inventors: San Yu, Veluchamy Palaniappagounder, Pratima Addepalli, Imran Khan
  • Patent number: 9269849
    Abstract: A photovoltaic device includes a substrate, a transparent conductive oxide, an n-type window layer, a p-type absorber layer and an electron reflector layer. The electron reflector layer may include zinc telluride doped with copper telluride, zinc telluride alloyed with copper telluride, or a bilayer of multiple layers containing zinc, copper, cadmium and tellurium in various compositions. A process for manufacturing a photovoltaic device includes forming a layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process includes forming an electron reflector layer over a p-type absorber layer.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: February 23, 2016
    Assignee: First Solar, Inc.
    Inventors: San Yu, Veluchamy Palaniappagounder, Pratima Addepalli, Imran Khan
  • Publication number: 20150004743
    Abstract: A method to improve operation of a CdTe-based photovoltaic device is disclosed, the method comprising the steps of depositing a semiconductor absorber layer adjacent to a substrate, depositing a semiconductor buffer layer adjacent to the semiconductor layer, and annealing at least one of the semiconductor absorber layer and the semiconductor buffer layer with one of a laser and a flash lamp.
    Type: Application
    Filed: June 27, 2014
    Publication date: January 1, 2015
    Inventors: Pratima Addepalli, Benyamin Buller, Markus Gloeckler, Akhlesh Gupta, David Hwang, Andrei Los, Rick Powell, Rui Shao, Gang Xiong, Ming Lun Yu, San Yu, Zhibo Zhao
  • Publication number: 20140284750
    Abstract: A photovoltaic device includes a substrate, a transparent conductive oxide, an n-type window layer, a p-type absorber layer and an electron reflector layer. The electron reflector layer may include zinc telluride doped with copper telluride, zinc telluride alloyed with copper telluride, or a bilayer of multiple layers containing zinc, copper, cadmium and tellurium in various compositions. A process for manufacturing a photovoltaic device includes forming a layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process includes forming an electron reflector layer over a p-type absorber layer.
    Type: Application
    Filed: March 20, 2014
    Publication date: September 25, 2014
    Applicant: FIRST SOLAR, INC.
    Inventors: San Yu, Veluchamy Palaniappagounder, Pratima Addepalli, Imran Khan
  • Publication number: 20140261667
    Abstract: A back electrode for a PV device and method of formation are disclosed. A ZnTe material is provided over an absorber material and a MoNx material is provided over the ZnTe material. A Mo material may also be included in the back electrode above or below the MoNx layer and a metal layer may be also provided over the MoNx layer.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 18, 2014
    Applicant: FIRST SOLAR, INC.
    Inventors: Benyamin Buller, Igor Sankin, Long Cheng, Jigish Trivedi, Jianjun Wang, Kieran Tracy, Scott Christensen, Gang Xiong, Markus Gloeckler, San Yu
  • Publication number: 20140273334
    Abstract: A method to improve CdTe-based photovoltaic device efficiency is disclosed, the method including steps for removing surface contaminants from a semiconductor absorber layer prior to the deposition or formation of a back contact layer on the semiconductor absorber layer, the surface contaminants removed using at least one of a dry etching process and a wet etching process.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Inventors: Scott Christensen, Pawel Mrozek, Gang Xiong, San Yu
  • Patent number: 8664027
    Abstract: A method of LED manufacturing is disclosed. A coating is applied to a mesa. This coating may have different thicknesses on the sidewalls of the mesa compared to the top of the mesa. Ion implantation into the mesa will form implanted regions in the sidewalls in one embodiment. These implanted regions may be used for LED isolation or passivation.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: March 4, 2014
    Assignee: Varian Semiconductor Associates, Inc.
    Inventors: San Yu, Atul Gupta
  • Patent number: 8658513
    Abstract: An improved method of creating LED arrays is disclosed. A p-type layer, multi-quantum well and n-type layer are disposed on a substrate. The device is then etched to expose portions of the n-type layer. To create the necessary electrical isolation between adjacent LEDs, an ion implantation is performed to create a non-conductive implanted region. In some embodiments, an implanted region extends through the p-type layer, MQW and n-type layer. In another embodiment, a first implanted region is created in the n-type layer. In addition, a second implanted region is created in the p-type layer and multi-quantum well immediately adjacent to etched n-type layer. In some embodiments, the ion implantation is done perpendicular to the substrate. In other embodiments, the implant is performed at an angle.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: February 25, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Fareen Adeni Khaja, Deepak Ramappa, San Yu, Chi-Chun Chen
  • Patent number: 8597962
    Abstract: An improved method of fabricating a vertical semiconductor LED is disclosed. Ions are implanted into the LED to create non-conductive regions, which facilitates current spreading in the device. In some embodiments, the non-conductive regions are located in the p-type layer. In other embodiments, the non-conductive layer may be in the multi-quantum well or n-type layer.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: December 3, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: San Yu, Chi-Chun Chen
  • Publication number: 20120238046
    Abstract: A method of LED manufacturing is disclosed. A coating is applied to a mesa. This coating may have different thicknesses on the sidewalls of the mesa compared to the top of the mesa. Ion implantation into the mesa will form implanted regions in the sidewalls in one embodiment. These implanted regions may be used for LED isolation or passivation.
    Type: Application
    Filed: February 2, 2012
    Publication date: September 20, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: San Yu, Atul Gupta
  • Patent number: 8263422
    Abstract: An improved method of creating LEDs is disclosed. Rather than using a dielectric coating to separate the bond pads from the top surface of the LED, this region of the LED is implanted with ions to increase its resistivity to minimize current flow therethrough. In another embodiment, a plurality of LEDs are produced on a single substrate by implanting ions in the regions between the LEDs and then etching a trench, where the trench is narrower than the implanted regions and positioned within these regions. This results in a trench where both sides have current confinement capabilities to reduce leakage.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: September 11, 2012
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: San Yu, Chi-Chun Chen