Abstract: A nonvolatile semiconductor memory device includes a memory cell array. The memory cell array includes conducting layers, semiconductor layers, variable resistance films, and first wirings. The conducting layers are laminated in a first direction perpendicular to a substrate, and extend in a second direction parallel to the substrate. The semiconductor layers extend in the first direction. The variable resistance films are disposed at intersection points of the conducting layers and the semiconductor layers. Each first wiring is opposed to the semiconductor layer via a gate insulating film. The first wirings extend in the first direction. Each variable resistance film has a first thickness at a first part. The first thickness is in a direction from the conducting layers to the semiconductor layer. The variable resistance film has a second thickness at a second part. The second part is far from the substrate more than the first part. The second thickness is smaller than the first thickness.

Abstract: According to an embodiment, a simulation method for resistance variations of a plurality of wires includes creating a numerical expression model for the resistance that is a function of parameters of a cross-sectional shape of the wire, based on the resistance calculated in a Monte Carlo Simulation, dividing each of the wires into a plurality of small elements in a length direction, calculating the resistance of each of the small elements by assigning the parameters of the cross-sectional shape characterizing the cross-sectional shape of each of the small elements to the numerical expression model, and calculating a sum of the resistances of the small elements in each of the wires.

Abstract: According to one embodiment, a method of simulating a manufacturing process of a structure including adjacent components, the method includes causing a computer to perform operations of: importing mesh and material data set for each component; specifying, as a calculation target, a region in a first component in which impurities are to be diffused among the components; setting a virtual film of a desired thickness in contact with the region whose material is the same as that of a second component in contact with the specified calculation target; setting boundary conditions at interface between the region and the virtual film, based on the material data; incorporating the boundary conditions into diffusion equations to solve the diffusion equations of the region and the virtual film; and bringing data on the concentration of impurities of the region obtained by the calculation into data on the structure before the specification of the region.

Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.

Abstract: In one embodiment, there is provided an ion implanting simulating method of implanting incident particles into a substrate, and gaining stationary position coordinates of each of the incident particles in the substrate, thereby calculating the distribution of the incident particles in the substrate. In the method, the followings are repeated desired times by a computer: implanting one of the incident particles into the substrate; calculating the trace of the incident particle traveling in the substrate while undergoing collision with an atom contained in the substrate repeatedly, and the energy lost from the incident particle by the collision, based on a beforehand-inputted composition of the substrate, thereby calculating stationary position coordinates of the incident particle; and renewing the composition of the substrate in accordance with a matter that the substrate contains the implanted incident particle.

Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.

Abstract: According to one embodiment, a method of simulating a manufacturing process of a structure including adjacent components, the method includes causing a computer to perform operations of: importing mesh and material data set for each component; specifying, as a calculation target, a region in a first component in which impurities are to be diffused among the components; setting a virtual film of a desired thickness in contact with the region whose material is the same as that of a second component in contact with the specified calculation target; setting boundary conditions at interface between the region and the virtual film, based on the material data; incorporating the boundary conditions into diffusion equations to solve the diffusion equations of the region and the virtual film; and bringing data on the concentration of impurities of the region obtained by the calculation into data on the structure before the specification of the region.

Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.

Abstract: A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.

Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.

Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.

Abstract: The group creation part divides n ion particles into groups of a group G1, a group G2, . . . , and a group Gk. The individual area setting part sets an initial condition calculation area 1a, as an individual area of the group G1, and makes the calculation part calculate movement of the ion particle. Then, one by one, the individual area setting part sets an individual area of a group Gi+1, based on a range Rp, a dispersion ?L, etc. indicating a calculation result of an ion particle belonging to the group Gi. Further, the individual area setting part implants an ion particle belonging to the group Gi+1 into the individual area of the group Gi+1 and makes the calculation part calculate movement of the implanted ion particle.

Abstract: A semiconductor device comprising at least one FET formed on the semiconductor substrate, wherein the FET comprises a source region, a drain region, a channel region formed between the source and drain regions and including a plurality of projected epitaxial silicon regions arranged in a width direction of the channel region, each of the projected epitaxial silicon regions having a triangular ridge portion, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film.

Abstract: A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.

Abstract: An aspect of the present invention provides a method of carrying out a simulation with simulation data, including, determining whether or not the simulation data includes boundary conditions set for a boundary of a calculation area set for the simulation, computing the influence of the boundary conditions on the inside of the calculation area if the simulation data includes the boundary conditions, displaying the influence of the boundary conditions on the inside of the calculation area, prompting to enter an instruction whether or not the boundary conditions are changed, and if an instruction to make no change in the boundary conditions is entered, carrying out the simulation with the simulation data.

Abstract: A semiconductor device comprising at least one FET formed on the semiconductor substrate, wherein the FET comprises a source region, a drain region, a channel region formed between the source and drain regions and including a plurality of projected epitaxial silicon regions arranged in a width direction of the channel region, each of the projected epitaxial silicon regions having a triangular ridge portion, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film.

Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.

Abstract: A semiconductor memory device comprising a semiconductor substrate, element isolating regions formed on the semiconductor substrate, an element forming region provided between the element isolating regions on the semiconductor substrate, the element forming region having a protruding portion, a transistor having a channel formed in the protruding portion of the element forming region, and a capacitor formed in or on the semiconductor substrate to be connected to the transistor, wherein the protruding portion in the element forming region includes first and second inclined and opposed planes arranged along a channel width direction of the transistor, and an upper plane provided between the first and second inclined planes.

Abstract: There is provided a semiconductor device which includes a projecting semiconductor layer provided on a substrate and having a first side surface and a second side surface opposed to the first side surface, a first gate insulating film provided on the semiconductor layer, a first gate electrode provided on the first gate insulating film, a first and a second diffusion layers provided on respective sides of the first gate electrode and in the semiconductor layer, a first insulating film provided on the first side surface, and a first conductive layer electrically connected to the first gate electrode and provided below the first and second diffusion layers and on a side surface of the first insulating film.

Abstract: The group creation part divides n ion particles into groups of a group G1, a group G2, . . . , and a group Gk. The individual area setting part sets an initial condition calculation area 1a, as an individual area of the group G1, and makes the calculation part calculate movement of the ion particle. Then, one by one, the individual area setting part sets an individual area of a group Gi+1, based on a range Rp, a dispersion ?L, etc. indicating a calculation result of an ion particle belonging to the group G1. Further, the individual area setting part implants an ion particle belonging to the group Gi+1 into the individual area of the group Gi+1 and makes the calculation part calculate movement of the implanted ion particle.