Patents by Inventor Sandeep Bhutani
Sandeep Bhutani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11087096Abstract: A system and method for reducing incident alerts for an enterprise environment are described. In one embodiment, a method of reducing incident alerts for an enterprise environment includes receiving a plurality of historical incident alerts associated with previous incidents associated with nodes within an enterprise environment. The method includes extracting from a first subset of the historical incident alerts a plurality of rules to generate a rule knowledge base and analyzing a second subset of the historical incident alerts against the plurality of rules to identify candidate incidents alerts as potential dead-end tickets. The method also includes providing feedback on the candidate incident alerts to confirm or deny that the alert is a dead-end ticket. Based on the feedback, a prescriptive avoidance rule set is generated to identify an incident alert as a dead-end ticket and eliminate the dead-end tickets from submitted incident alerts.Type: GrantFiled: March 4, 2019Date of Patent: August 10, 2021Assignee: Accenture Global Solutions LimitedInventors: Ramkumar Balasubramanian, Sandeep Bhutani, Chandrasekhar Pilla, Shallu Gupta, Sekhar Naga Venkata Maddula
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Patent number: 10904072Abstract: A system and method to intelligently formulate automation strategies for technology infrastructure operations are disclosed. The system and method include analyzing infrastructure issue data from support tickets and predicting automation solutions. A cost-benefit analysis is then performed on the automation solutions. Solutions can be ranked and recommended according to the cost-benefit analysis.Type: GrantFiled: December 31, 2018Date of Patent: January 26, 2021Assignee: Accenture Global Solutions LimitedInventors: Ramkumar Balasubramanian, Sandeep Bhutani, Chandrasekhar Pilla, Shallu Gupta, Sekhar Naga Venkata Maddula
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Publication number: 20200285697Abstract: A system and method for reducing incident alerts for an enterprise environment are described. In one embodiment, a method of reducing incident alerts for an enterprise environment includes receiving a plurality of historical incident alerts associated with previous incidents associated with nodes within an enterprise environment. The method includes extracting from a first subset of the historical incident alerts a plurality of rules to generate a rule knowledge base and analyzing a second subset of the historical incident alerts against the plurality of rules to identify candidate incidents alerts as potential dead-end tickets. The method also includes providing feedback on the candidate incident alerts to confirm or deny that the alert is a dead-end ticket. Based on the feedback, a prescriptive avoidance rule set is generated to identify an incident alert as a dead-end ticket and eliminate the dead-end tickets from submitted incident alerts.Type: ApplicationFiled: March 4, 2019Publication date: September 10, 2020Inventors: Ramkumar Balasubramanian, Sandeep Bhutani, Chandrasekhar Pilla, Shallu Gupta, Sekhar Naga Venkata Maddula
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Publication number: 20200162312Abstract: A system and method to intelligently formulate automation strategies for technology infrastructure operations are disclosed. The system and method include analyzing infrastructure issue data from support tickets and predicting automation solutions. A cost-benefit analysis is then performed on the automation solutions. Solutions can be ranked and recommended according to the cost-benefit analysis.Type: ApplicationFiled: December 31, 2018Publication date: May 21, 2020Inventors: Ramkumar Balasubramanian, Sandeep Bhutani, Chandrasekhar Pilla, Shallu Gupta, Sekhar Naga Venkata Maddula
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Patent number: 8539411Abstract: An apparatus and method to characterize a new process using an improved delay calculation. Multiple derating factors are used for different STA sign off corners that have a base corner with two pairs of off-corners. The approach of the present invention does not add any extra work in cell library characterization, while in the mean it increases the accuracy of the delay calculation and the library generation at corners other than standard corners.Type: GrantFiled: February 26, 2008Date of Patent: September 17, 2013Assignee: LSI CorporationInventors: Qian Cui, Sandeep Bhutani
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Patent number: 8516425Abstract: A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.Type: GrantFiled: July 9, 2012Date of Patent: August 20, 2013Assignee: LSI CorporationInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykih, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin
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Publication number: 20120278783Abstract: A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.Type: ApplicationFiled: July 9, 2012Publication date: November 1, 2012Applicant: LSI CORPORATIONInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykh, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin
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Patent number: 8239813Abstract: A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.Type: GrantFiled: June 30, 2011Date of Patent: August 7, 2012Assignee: LSI CorporationInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykih, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin
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Patent number: 8156466Abstract: An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. the elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.Type: GrantFiled: December 19, 2008Date of Patent: April 10, 2012Assignee: LSI CorporationInventors: Weiqing Guo, Sandeep Bhutani
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Publication number: 20110258587Abstract: A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.Type: ApplicationFiled: June 30, 2011Publication date: October 20, 2011Applicant: LSI CORPORATIONInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykh, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin
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Patent number: 7996804Abstract: A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.Type: GrantFiled: January 17, 2008Date of Patent: August 9, 2011Assignee: LSI CorporationInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykih, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin
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Patent number: 7689965Abstract: A system, apparatus and method for generating extracted timing model files, such as macro library files, are disclosed. A user interface or data template is provided to an engineer that allows for the population of data within particular fields related to timing characteristics of an IP block, cell or core. Various types of data and fields may be provided into the user interface or data template. The location of relevant files, such as a cell or core netlist, may be provided within the template. Additionally, one or more modes may be selected by the user to define the manner in which the ETM file(s) are to be generated. An ETM file is automatically generated using the information provided in the data template.Type: GrantFiled: February 9, 2006Date of Patent: March 30, 2010Assignee: LSI CorporationInventors: Peter Lindberg, Richard K. Kirchner, Sandeep Bhutani
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Patent number: 7661083Abstract: A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design is passed when the probabilistic noise does not exceed the voltage threshold. When the probabilistic noise does exceed the threshold, then an effective noise at a desired mean time to failure is computed, and the effective noise is checked against the voltage threshold. The victim net design is passed when the effective noise does not exceed the voltage threshold, and failed when the effective noise does exceed the threshold.Type: GrantFiled: March 11, 2008Date of Patent: February 9, 2010Assignee: LSI CorporationInventors: Payman Zarkesh-Ha, Sandeep Bhutani, Weiqing Guo
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Publication number: 20090217226Abstract: An apparatus and method to characterize a new process using an improved delay calculation. Multiple derating factors are used for different STA sign off corners that have a base corner with two pairs of off-corners. The approach of the present invention does not add any extra work in cell library characterization, while in the mean it increases the accuracy of the delay calculation and the library generation at corners other than standard corners.Type: ApplicationFiled: February 26, 2008Publication date: August 27, 2009Inventors: Qian Cui, Sandeep Bhutani
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Patent number: 7577928Abstract: A system, apparatus and method for generating and validating extracted timing model files, such as macro library files, are disclosed. A user interface or data template is provided to an engineer that allows for the population of data within particular fields related to timing characteristics of an IP block, cell or core. An extracted timing model file is generated and a validation procedure is performed. This validation procedure may include comparing the information with the file to a test bench have a plurality of test points. In particular, data provided by the engineer is checked against multiple criteria to ensure that this data is valid and/or falls within an appropriate value range constraints. After the validation procedure has completed, the engineer is provided a summary of the validation results.Type: GrantFiled: March 15, 2006Date of Patent: August 18, 2009Assignee: LSI Logic CorporationInventors: Peter Lindberg, Richard K. Kirchner, Sandeep Bhutani
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Publication number: 20090187873Abstract: A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.Type: ApplicationFiled: January 17, 2008Publication date: July 23, 2009Applicant: LSI CorporationInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykh, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin
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Publication number: 20090158228Abstract: An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. the elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.Type: ApplicationFiled: December 19, 2008Publication date: June 18, 2009Applicant: LSI CORPORATIONInventors: Weiqing Guo, Sandeep Bhutani
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Patent number: 7539960Abstract: An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. The elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.Type: GrantFiled: June 1, 2006Date of Patent: May 26, 2009Assignee: LSI CorporationInventors: Weiqing Guo, Sandeep Bhutani
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Publication number: 20080163145Abstract: A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design is passed when the probabilistic noise does not exceed the voltage threshold. When the probabilistic noise does exceed the threshold, then an effective noise at a desired mean time to failure is computed, and the effective noise is checked against the voltage threshold. The victim net design is passed when the effective noise does not exceed the voltage threshold, and failed when the effective noise does exceed the threshold.Type: ApplicationFiled: March 11, 2008Publication date: July 3, 2008Applicant: LSI CORPORATIONInventors: Payman Zarkesh-Ha, Sandeep Bhutani, Weiqing Guo
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Patent number: 7376918Abstract: A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design is passed when the probabilistic noise does not exceed the voltage threshold. When the probabilistic noise does exceed the threshold, then an effective noise at a desired mean time to failure is computed, and the effective noise is checked against the voltage threshold. The victim net design is passed when the effective noise does not exceed the voltage threshold, and failed when the effective noise does exceed the threshold.Type: GrantFiled: March 11, 2005Date of Patent: May 20, 2008Assignee: LSI CorporationInventors: Payman Zarkesh-Ha, Sandeep Bhutani, Weiqing Guo