Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a graphics processor. The apparatus may obtain an indication of data for a memory access process, wherein the data for the memory access process is associated with data processing. The apparatus may also determine whether space is available for the data and an address of the data in a cache. Further, the apparatus may store, based on space being available in the cache, the data and the address of the data in the cache; or refrain from storing, based on space being unavailable in the cache, the data and the address of the data in the cache.

Abstract: Aspects of the disclosure are directed to an adaptive cache memory buffer register reassignment. In accordance with one aspect, the disclosure includes incrementing a write hit-miss state based on a write address validation state and a write data validation state; incrementing a read hit-miss state based on a read address validation state and a read data validation state; computing a net mode count based on the write hit-miss state and the read hit-miss state; comparing the net mode count to a mode threshold value to update a plurality of mode toggle states; and generating an adaptive cache memory buffer register reassignment based on the plurality of mode toggle states.

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for interpolating a color for an interpolation point. A graphics processor may select a set of known points (known location, known color value) about an interpolation point. The processor may select a reference known point from the set of known points. The processor may determine a relative color value for each of the set of known points other than the selected reference known point based on a color difference between a corresponding known point and the selected reference known point. The processor may determine an interpolation color for the interpolation point based on the determined relative color value, the interpolation point, and a first known color value of the selected reference known point. The processor may output an indicator of the determined interpolation color for the interpolation point.

Abstract: A cache circuit includes read address registers to store memory addresses of data blocks requested in recent memory read transactions in a memory circuit and write address registers to store memory addresses of the data blocks recently written to the memory circuit. The cache circuit also includes data registers for storing data blocks corresponding to select memory addresses stored in the read address registers and the write address registers based on a pattern of recent memory transactions. The selection of memory addresses for which corresponding data blocks are stored in the data registers is based on a mode count that may be dynamically determined based on the memory addresses accessed in the most recent memory transactions. The mode count depends on whether a requested data block is stored in the data registers and whether the memory address is stored in the read address registers or the write address registers.