Abstract: A method includes training a timing flip-flop circuit positioned between a controller and a memory resource, providing a plurality of data signals and a plurality of clock signals to the timing flip-flop circuit to generate a plurality of output clock signals and a plurality of output data signals, serializing the plurality of output clock signals and the plurality of output data signals, and providing the serialized plurality of output clock signals and the serialized plurality of output data signals to one of the controllers or the memory resources.

Abstract: An apparatus includes a die with a first face, a second face opposite the first face, and a third face located between the first face and the second face, I/O cells coupled to the first face of a die, where the I/O cells are configured to be selectively bonded to a package by wirebonded interconnections at a first pitch or flip-chip interconnections at a second pitch that is larger than the first pitch, and a bond area including decoupling capacitors that is located between each I/O cell and the third face of the die.

Abstract: A performance characteristic monitoring circuitry includes a first delay circuitry providing a first delay path, where transmission of a data value over that first delay path incurs a first delay that varies in dependence on the performance characteristic. Reference delay circuitry is also included to provide a reference delay path, where transmission of the data value over the reference delay path incurs a reference delay. The reference delay circuitry includes components configured to provide a capacitive loading on the reference delay path in order to produce a self-compensating effect on the reference delay that causes the reference delay to be less sensitive than the first delay to variation in the performance characteristic. Comparison circuitry is then used to generate the output signal of the monitoring circuitry in dependence on a comparison of the first delay and the reference delay.

Abstract: A performance characteristic monitoring circuitry includes a first delay circuitry providing a first delay path, where transmission of a data value over that first delay path incurs a first delay that varies in dependence on the performance characteristic. Reference delay circuitry is also included to provide a reference delay path, where transmission of the data value over the reference delay path incurs a reference delay. The reference delay circuitry includes components configured to provide a capacitive loading on the reference delay path in order to produce a self-compensating effect on the reference delay that causes the reference delay to be less sensitive than the first delay to variation in the performance characteristic. Comparison circuitry is then used to generate the output signal of the monitoring circuitry in dependence on a comparison of the first delay and the reference delay.

Abstract: An integrated circuit 2 operates using a digital signal having a duty cycle. Duty cycle correction circuitry 26, 28, 30 operate under control of digital correction values which adjust the duty cycle of the digital signal to a target duty cycle. Periodically, detection of the duty cycle output from the duty cycle correction circuitry 26, 28, 30 is performed to determine whether or not this has drifted outside of a threshold range of duty cycles and if necessary the digital correction value is changed to bring the duty cycle back within the threshold range. The duty cycle correction circuitry 26, 28, 30 employs common mode logic stages 44, 46 and an auxiliary current path 48 which is controlled in its impedance by the digital correction value. The auxiliary current path 48 applies an offset voltage within the common mode logic stage 44 which adjusts the duty cycle of the digital signal represented by the differential signals propagating through the common mode logic stage 44.

Abstract: An integrated circuit 2 includes a receiver circuit 4 for receiving an input signal PAD and converting this to an output signal OUT. Conduction path circuitry 14 couples an input 10 to a first node 16. Buffer circuitry 18 is coupled between the first node 16 and an output 12 carrying the output signal Out. The conduction path circuitry comprises a first PMOS transistor 24 and a second PMOS transistor 26 connected between the input 10 and the first node 16. A first NMOS transistor 28 is connected between the input 10 and the first node 16. The gate of the second PMOS transistor 26 is coupled to the output 12 to directly receive the output signal and thereby achieve rapid cut off of the charging of the node 16 when the input voltage rises beyond a certain level which switches the buffer circuitry 18.

Abstract: An integrated circuit 2 includes a receiver circuit 4 for receiving an input signal PAD and converting this to an output signal OUT. Conduction path circuitry 14 couples an input 10 to a first node 16. Buffer circuitry 18 is coupled between the first node 16 and an output 12 carrying the output signal Out. The conduction path circuitry comprises a first PMOS transistor 24 and a second PMOS transistor 26 connected between the input 10 and the first node 16. A first NMOS transistor 28 is connected between the input 10 and the first node 16. The gate of the second PMOS transistor 26 is coupled to the output 12 to directly receive the output signal and thereby achieve rapid cut off of the charging of the node 16 when the input voltage rises beyond a certain level which switches the buffer circuitry 18.

Abstract: A low voltage differential signalling driver is provided in which a first output node and a second output node provide a differential signal. First differential steering switch circuitry is switched in dependence on a differential input signal to selectively connect the first output node to a voltage supply via a current source, while second differential steering circuitry is switched in dependence on an inverse version of the differential input signal to connect the second output node to the voltage supply via the current source. Slew control circuitry is provided, configured to establish a current discharge path for the current source during the polarity transition of the differential input signal, thus maintaining a symmetric slew rate of the output signals at the first output node and second output node.

Abstract: A low voltage differential signalling driver is provided in which a first output node and a second output node provide a differential signal. First differential steering switch circuitry is switched in dependence on a differential input signal to selectively connect the first output node to a voltage supply via a current source, whilst second differential steering circuitry is switched in dependence on an inverse version of the differential input signal to connect the second output node to the voltage supply via the current source. Slew control circuitry is provided, configured to establish a current discharge path for the current source during the polarity transition of the differential input signal, thus maintaining a symmetric slew rate of the output signals at the first output node and second output node.