Abstract: Apparatuses and methods for accessing a memory cell are described. An example apparatus includes a first voltage circuit coupled to a node and is configured to provide a first voltage to the node and includes a second voltage circuit coupled to a node and is configured to provide a second voltage to the node. A memory cell is coupled to first and second access lines. A decoder circuit is coupled to the node and the first access line, and is configured to selectively couple the first access line to the node. The first voltage circuit is configured to provide the first voltage to the node before the second voltage circuit provides the second voltage to the node, and the second voltage circuit stops providing the second voltage before the node reaches the second voltage.

Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods of programming the nonvolatile memory including dual demarcation voltage sensing before writes.

Abstract: Apparatuses and methods for accessing a memory cell are described. An example apparatus includes a first voltage circuit coupled to a node and is configured to provide a first voltage to the node and includes a second voltage circuit coupled to a node and is configured to provide a second voltage to the node. A memory cell is coupled to first and second access lines. A decoder circuit is coupled to the node and the first access line, and is configured to selectively couple the first access line to the node. The first voltage circuit is configured to provide the first voltage to the node before the second voltage circuit provides the second voltage to the node. and the second voltage circuit stops providing the second voltage before the node reaches the second voltage.

Abstract: Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.

Abstract: Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.

Abstract: A multistage read can dynamically change wordline capacitance as a function of threshold voltage of a memory cell being read. The multistage read can reduce current spikes and reduce the heating up of a memory cell during a read. A memory device includes a global wordline driver to connect a wordline of a selected memory cell to the sensing circuit, and a local wordline driver local to the memory cell. After the wordline is charged to a read voltage, control logic can selectively enable and disable a portion or all of the global wordline driver and the local wordline driver in conjunction with applying different discrete voltage levels to the bitline to perform a multistage read.

Abstract: An apparatus and method are disclosed for providing a kicker function for non-volatile memory drain bias. According to one embodiment, the kicker function is provided by a high performance transistor that is activated by a kicker enable signal, providing a kicker function for non-volatile memory drain bias. According to one embodiment, the kicker function is provided by a high performance transistor that is activated by a kicker enable signal.

Abstract: In one embodiment, the invention is an apparatus. The apparatus includes a first drain bias network having an input suitable to couple to a FLASH cell. The apparatus also includes a second drain bias network having an input suitable to couple to a FLASH cell. The apparatus further includes an equalization circuit having a first node coupled to the input of the first drain bias network and having a second node coupled to the input of the second drain bias network and having a control signal to control operation of the equalization circuit.

Abstract: An apparatus is disclosed for providing a load for a non-volatile memory drain bias circuit. Under an embodiment, a load for a non-volatile memory drain bias circuit comprises a column load and a current mirror, a reference voltage for the current mirror being a sample and hold voltage reference. The column load and the current mirror are coupled to a cascode device.

Abstract: An apparatus and method are disclosed for providing drain bias for non-volatile memory. According to one embodiment, the drain bias is provided utilizing a drain bias circuit that is referenced by a static voltage reference.

Abstract: In one embodiment, the invention is an apparatus. The apparatus includes a first drain bias network having an input suitable to couple to a FLASH cell. The apparatus also includes a second drain bias network having an input suitable to couple to a FLASH cell. The apparatus further includes an equalization circuit having a first node coupled to the input of the first drain bias network and having a second node coupled to the input of the second drain bias network and having a control signal to control operation of the equalization circuit.

Abstract: According to the invention, an apparatus and method are disclosed for sensing the contents of non-volatile memory. According to one embodiment, a set of local sensing circuits is used to read the logical values stored in memory cells contained within a partition of a non-volatile memory device.

Abstract: An apparatus and method are disclosed for providing a load for non-volatile memory drain bias. According to one embodiment, a load comprising a column load and a current mirror is referenced using a sample and hold voltage reference.

Abstract: An apparatus and method are disclosed for providing a sample and hold voltage reference for non-volatile memory. According to one embodiment, the sample and hold voltage reference produces a reference voltage for a drain bias circuit of a memory cell.

Abstract: According to the invention, an apparatus and method are disclosed for sensing the contents of non-volatile memory. According to one embodiment, a set of local sensing circuits is used to read the logical values stored in memory cells contained within a partition of a non-volatile memory device.

Abstract: An apparatus and method are disclosed for providing a sample and hold voltage reference for non-volatile memory. According to one embodiment, the sample and hold voltage reference produces a reference voltage for a drain bias circuit of a memory cell.

Abstract: An apparatus and method are disclosed for providing a kicker function for non-volatile memory drain bias. According to one embodiment, the kicker function is provided by a high performance transistor that is activated by a kicker enable signal. providing a kicker function for non-volatile memory drain bias. According to one embodiment, the kicker function is provided by a high performance transistor that is activated by a kicker enable signal.

Abstract: An apparatus and method are disclosed for providing drain bias for non-volatile memory. According to one embodiment, the drain bias is provided utilizing a drain bias circuit that is referenced by a static voltage reference.

Abstract: In one embodiment, the invention is an apparatus. The apparatus includes a column load component and a current mirror coupled in parallel with the column load component. The column load component is capable of being coupled to a FLASH cell and a sense amplifier.

Abstract: An apparatus for protecting memory blocks in a block-based flash Erasable Programmable Read Only Memory (EPROM) device is disclosed. A non-volatile memory array includes a number of blocks that are capable of being placed in a locked state or an unlocked state. A volatile lock register and transmits a write protect signal and a volatile lock-down register are coupled to a lockable block in the volatile memory array. A hardware override line is coupled to both the lock register and the lock-down register. The hardware override line temporarily overrides operation of the lock-down register when it transmits a signal at a first logic state. The lock down register may be used to prevent programming of an associated lock register. The lock registers and lock down registers may be embodied in static access memory (SRAM) circuits.