Abstract: Approaches for data compression involve a compression circuit packing non-zero data elements of a succession of words of a plurality of blocks into packed words by packing non-zero data elements of one or more words of the succession in each packed word, and restricting each packed word to data elements of one uncompressed block. The compression circuit writes each packed word in a RAM and within a compressed address range associated with the uncompressed block when the packed word is full of non-zero data elements, or before the packed word is full if the next input word is of another uncompressed block.

Abstract: A memory controller is provided, which includes a request input for receiving successive memory access requests and a memory interface configured for coupling to a memory device having a plurality of banks. The memory controller has a bank control circuit, which generates a bank access command on the memory interface for a respective one of the banks in response to each memory access request to that bank. The bank control circuit has a plurality of selectable operating modes, including a Request Count Mode. When in the Request Count Mode, the bank control circuit generates a bank precharge command on the memory interface for the respective bank if none of a predetermined number of subsequent ones of the memory access requests is to that bank.