Abstract: A circuit is disclosed which allows an IN-Test to be performed on an integrated circuit (IC) without having to stop the external clock sources by disabling the IC's internal phase-locked loops. Information indicative of the IC's clock mode and of the desired stop mode is contained within the IC's clock control register. In one embodiment, the internal clocks may be stopped in either of three stop modes while operating in one of three clock modes. When it is desired to stop the IC's internal clocks, the clock control register provides a stop instruction signal STOP.sub.-- INSTR to a clock control circuit which, depending upon the particular stop mode and clock mode encoded in signal STOP.sub.-- INSTR by the clock control register, asserts a enabling signal to a disable clock circuit.

Abstract: Circuits and methods of testing an integrated circuit die are disclosed. Active logic setting circuits are incorporated into input cells of a die. During testing, the active logic setting circuits weakly drive the input cells to a definite logic level. Therefore, the necessity of connecting probes to all of the input pads to prevent floating signals in the die is eliminated. Furthermore, during normal operations the active logic setting circuits have little or no effect on the performance of the die.