Abstract: With Successive Approximation Register (SAR) analog-to-digital converters (ADCs), there are several different architectures. One of these architectures is a “convert and shut down” architecture, where an internal amplifier is powered down during the sampling phase to reduce power consumption. This powering down comes at a price in that a portion of the convert phase is lost waiting for the amplifier to be powered back up. Here, an apparatus is provided that makes use of the entire convert phase by coarsely resolving a few bits during the period in which the amplifier is powering up to have an increased resolution over conventional SAR ADCs with “convert and shut down” architecture, while maintaining low power consumption.

Abstract: With Successive Approximation Register (SAR) analog-to-digital converters (ADCs), there are several different architectures. One of these architectures is a “convert and shut down” architecture, where an internal amplifier is powered down during the sampling phase to reduce power consumption. This powering down comes at a price in that a portion of the convert phase is lost waiting for the amplifier to be powered back up. Here, an apparatus is provided that makes use of the entire convert phase by coarsely resolving a few bits during the period in which the amplifier is powering up to have an increased resolution over conventional SAR ADCs with “convert and shut down” architecture, while maintaining low power consumption.

Abstract: An apparatus is provided. The apparatus comprises a sample switch, a sampling capacitor, an amplifier, feedback branches, a second hold switch, an N-bit converter pair, a third hold switch, and an M-bit converter pair. The sample receives an input signal and is actuated by a sample signal. The sampling capacitor is coupled to the sample switch. The amplifier has a first input terminal that is coupled to the sampling capacitor. The feedback branches are coupled between the output terminal of the amplifier and the first input terminal of the amplifier, with each feedback branch including a feedback capacitor, and a first hold switch that is coupled to the feedback capacitor. The second hold switch is coupled to the sampling switch. The N-bit converter pair is coupled to the sampling switch and to the second hold switch. The third hold switch is coupled to at least one of the feedback branches, and the M-bit converter pair is coupled to the output terminal of the amplifier and to the third hold switch.

Abstract: An apparatus is provided. The apparatus comprises a sample switch, a sampling capacitor, an amplifier, feedback branches, a second hold switch, an N-bit converter pair, a third hold switch, and an M-bit converter pair. The sample receives an input signal and is actuated by a sample signal. The sampling capacitor is coupled to the sample switch. The amplifier has a first input terminal that is coupled to the sampling capacitor. The feedback branches are coupled between the output terminal of the amplifier and the first input terminal of the amplifier, with each feedback branch including a feedback capacitor, and a first hold switch that is coupled to the feedback capacitor. The second hold switch is coupled to the sampling switch. The N-bit converter pair is coupled to the sampling switch and to the second hold switch. The third hold switch is coupled to at least one of the feedback branches, and the M-bit converter pair is coupled to the output terminal of the amplifier and to the third hold switch.

Abstract: According to an aspect of the present invention, samples of an input signal are provided with reduced distortion, when the input signal is received from a lead terminal offering lead inductance on an input path. Such a feature is achieved by charging a energy storage element to a value proportional to the input signal using a portion of charging energy received through a path having less lead inductance compared to the path connecting the input signal to the energy storage element. Thus, the energy drawn through the lead impedance is reduced, thereby reducing the magnitude of the distortion caused.

Abstract: A method for reducing transmit echo in a DSL modem comprises selecting at least one cancellation device of a plurality of cancellation devices. An attenuation signal is generated using the selected cancellation device. At least a portion of transmit echo is removed from a receive signal using the attenuation signal.

Abstract: Ensuring sufficient bias current is provided to a portion of a circuit containing low voltage transistors operating with a high supply voltage. Such a sufficient bias current may be ensured by generating a primary bias current from a low supply voltage and a backup bias current from a high supply voltage, and providing the backup bias current as the bias current if the primary bias current is not present. The primary bias current may be provided as the bias current when the low supply voltage is available. Thus, the backup bias current is provided as bias current in case of undesirable supply sequencing.

Abstract: Using an operational amplifier with a low gain in a closed loop amplifier circuit, and correcting for errors (i.e., deviation from the output of an ideal closed loop amplifier using an operational amplifier with infinite gain) that would result from the use of the operational amplifier with low gain. In an embodiment implemented in relation to an analog to digital converter (ADC), a mathematical operation is performed on the digital code(s) generated by the ADC to generate a corrected code corresponding to an analog sample.

Abstract: A method for reducing transmit echo in a DSL modem comprises selecting at least one cancellation device of a plurality of cancellation devices. An attenuation signal is generated using the selected cancellation device. At least a portion of transmit echo is removed from a receive signal using the attenuation signal.