Abstract: An ultrasound system includes a transmit-receive switch. The transmit-receive switch includes a combined transmit-receive and return-to-zero (RTZ) path. The combined transmit-receive and RTZ path includes a transistor with a first current terminal, a second current terminal, and a control terminal. The second current terminal of the transistor is coupled to a ground node via a first switch and is coupled to a receive node via a second switch. The ultrasound system also includes a receiver front-end circuit coupled to the receive node.

Abstract: An ultrasound system includes a transmit-receive switch. The transmit-receive switch includes a combined transmit-receive and return-to-zero (RTZ) path. The combined transmit-receive and RTZ path includes a transistor with a first current terminal, a second current terminal, and a control terminal. The second current terminal of the transistor is coupled to a ground node via a first switch and is coupled to a receive node via a second switch. The ultrasound system also includes a receiver front-end circuit coupled to the receive node.

Abstract: A delay line control circuit includes a pseudo-random number generator and a random phase generator circuit coupled to the pseudo-random number generator. The pseudo-random number generator is configured to produce a predetermined sequence of pseudo-random values. The random phase generator circuit is configured to randomize an access sequence for capacitors of a delay line. The random phase generator circuit includes a sequence register, an adder, and gating circuitry. The sequence register is configured to a store a value identifying one of the capacitors to be accessed. The adder is coupled to the sequence register, and is configured to increment the value stored in sequence register. The gating circuitry is coupled to the pseudo-random number generator and the adder. The gating circuitry is configured to pass one of the pseudo-random values to the adder for addition to the value stored in the sequence register.

Abstract: Methods and apparatus for reducing a transient glitch in ultrasound applications are disclosed. An example apparatus includes a transducer to (A) output a signal during a transmit phase and (B) receive a reflected signal corresponding to the signal during a receive phase; a receiver switch coupled to the transducer at a first node, the receiver switch to (A) open during the transmit phase and (B) close during the receive phase; and a clamp coupled to the transducer at the first node, the clamp to provide a high impedance during the transmit phase and the receive phase and provide a low impedance during a transient phase.

Abstract: A radio frequency transmitter includes an upconverter that outputs in-phase (I) and quadrature (Q) signals, a digital timing offset circuit, first and second digital-to-analog converters (DACs), an analog timing offset removal circuit, first and second pulse shapers, and an adder. The digital timing offset circuit introduces a time offset between the I and Q signals. The first and second DACs output analog I and Q signals, respectively, and have first and second clock signals, respectively. The first and second clock signals have the same frequency and are offset relative to each other by the time offset. The analog timing offset removal circuit removes the time offset between the analog I and Q signals. The first and second pulse shapers receive the analog I and Q signals, respectively, and output pulse-shaped I and Q signals. The adder receives the pulse-shaped I and Q signals and outputs an intermediate frequency signal.

Abstract: A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

Abstract: In described examples, a charge sensitive amplifier (CSA) generates an integrated signal in response to a current signal. A high pass filter is coupled to the CSA and receives the integrated signal and an inverse of an event signal, the high pass filter generates a coarse signal. An active comparator is coupled to the high pass filter and receives the coarse signal and a primary reference voltage signal, the active comparator generates the event signal.

Abstract: Analog gain correction circuitry and analog switching clock edge timing correction circuitry can provide coarse correction of interleaving errors in radio-frequency digital-to-analog converters (RF DACs), such as may be used in 5G wireless base stations. The analog correction can be supplemented by digital circuitry configured to “pre-cancel” an interleaving image by adding to a digital DAC input signal a signal equal and opposite to an interleaving image created by the interleaving DAC, such that the interleaving image is effectively mitigated. Error correction control parameters can be periodically adjusted for changes in temperature by a controller coupled to an on-chip temperature sensor. A model useful for understanding the sources of error in interleaving DACs is also described.

Abstract: In described examples, a circuit includes an integrator. The integrator generates a first signal responsive to an input signal. A trigger circuit is coupled to the integrator and receives the first signal. A charge dump circuit is coupled to the integrator and the trigger circuit. The trigger circuit modifies configuration of the charge dump circuit and the integrator when the first signal is greater than a first threshold.

Abstract: A system includes a Zero IF transmitter having a mixer and a programmable gain stage. The Zero IF transmitter also includes an intermediate stage between the mixer and the programmable gain stage, wherein the intermediate stage is configured to decouple the mixer and the programmable gain stage.

Abstract: The disclosure provides a receiver with high dynamic range. The receiver includes a photodiode that generates a current signal. A coupling capacitor is coupled to the photodiode, and generates a modulation signal in response to the current signal received from the photodiode. A sigma delta analog to digital converter (ADC) is coupled to the coupling capacitor, and generates a digital data in response to the modulation signal. A digital mixer is coupled to the sigma delta ADC, and generates an in-phase component and a quadrature component corresponding to the digital data. A processor is coupled to the digital mixer, and processes the in-phase component and the quadrature component corresponding to the digital data.

Abstract: Methods and apparatus for reducing a transient glitch in ultrasound applications are disclosed. An example apparatus includes a transducer to (A) output a signal during a transmit phase and (B) receive a reflected signal corresponding to the signal during a receive phase; a receiver switch coupled to the transducer at a first node, the receiver switch to (A) open during the transmit phase and (B) close during the receive phase; and a clamp coupled to the transducer at the first node, the clamp to provide a high impedance during the transmit phase and the receive phase and provide a low impedance during a transient phase.

Abstract: Methods and apparatus for reducing a transient glitch in ultrasound applications are disclosed. An example apparatus includes a transducer to (A) output a signal during a transmit phase and (B) receive a reflected signal corresponding to the signal during a receive phase; a receiver switch coupled to the transducer at a first node, the receiver switch to (A) open during the transmit phase and (B) close during the receive phase; and a clamp coupled to the transducer at the first node, the clamp to provide a high impedance during the transmit phase and the receive phase and provide a low impedance during a transient phase.

Abstract: A dark current compensation circuit comprises a first comparator having inputs for a detection signal and a first voltage, and a second comparator having inputs for the detection signal and a second voltage. The dark current compensation circuit also comprises a controller coupled to the first and second comparators, which has an input for an event signal. An adjustable current source is coupled to the controller and configured to generate a compensation current. The controller adjusts a value of the compensation current based on the first and second comparator outputs and maintains a constant value in response to the event signal indicating photons incident on a photon detector. In some implementations, the dark current compensation circuit further comprises an analog sub-circuit coupled to the adjustable current source and configured to receive the detection signal. The analog sub-circuit generates an analog compensation current in response to the detection signal.

Abstract: A delay line control circuit includes a pseudo-random number generator and a random phase generator circuit coupled to the pseudo-random number generator. The pseudo-random number generator is configured to produce a predetermined sequence of pseudo-random values. The random phase generator circuit is configured to randomize an access sequence for capacitors of a delay line. The random phase generator circuit includes a sequence register, an adder, and gating circuitry. The sequence register is configured to a store a value identifying one of the capacitors to be accessed. The adder is coupled to the sequence register, and is configured to increment the value stored in sequence register. The gating circuitry is coupled to the pseudo-random number generator and the adder. The gating circuitry is configured to pass one of the pseudo-random values to the adder for addition to the value stored in the sequence register.

Abstract: A delay line control circuit includes a pseudo-random number generator and a random phase generator circuit coupled to the pseudo-random number generator. The pseudo-random number generator is configured to produce a predetermined sequence of pseudo-random values. The random phase generator circuit is configured to randomize an access sequence for capacitors of a delay line. The random phase generator circuit includes a sequence register, an adder, and gating circuitry. The sequence register is configured to a store a value identifying one of the capacitors to be accessed. The adder is coupled to the sequence register, and is configured to increment the value stored in sequence register. The gating circuitry is coupled to the pseudo-random number generator and the adder. The gating circuitry is configured to pass one of the pseudo-random values to the adder for addition to the value stored in the sequence register.

Abstract: A dark current compensation circuit comprises a first comparator having inputs for a detection signal and a first voltage, and a second comparator having inputs for the detection signal and a second voltage. The dark current compensation circuit also comprises a controller coupled to the first and second comparators, which has an input for an event signal. An adjustable current source is coupled to the controller and configured to generate a compensation current. The controller adjusts a value of the compensation current based on the first and second comparator outputs and maintains a constant value in response to the event signal indicating photons incident on a photon detector. In some implementations, the dark current compensation circuit further comprises an analog sub-circuit coupled to the adjustable current source and configured to receive the detection signal. The analog sub-circuit generates an analog compensation current in response to the detection signal.

Abstract: A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

Abstract: A system includes a Zero IF transmitter having a mixer and a programmable gain stage. The Zero IF transmitter also includes an intermediate stage between the mixer and the programmable gain stage, wherein the intermediate stage is configured to decouple the mixer and the programmable gain stage.

Abstract: Analog gain correction circuitry and analog switching clock edge timing correction circuitry can provide coarse correction of interleaving errors in radio-frequency digital-to-analog converters (RF DACs), such as may be used in 5G wireless base stations. The analog correction can be supplemented by digital circuitry configured to “pre-cancel” an interleaving image by adding to a digital DAC input signal a signal equal and opposite to an interleaving image created by the interleaving DAC, such that the interleaving image is effectively mitigated. Error correction control parameters can be periodically adjusted for changes in temperature by a controller coupled to an on-chip temperature sensor. A model useful for understanding the sources of error in interleaving DACs is also described.