Abstract: Aspects of the disclosed technology relate to techniques of parasitic extraction using compact representation of process calibration data. Geometric information of a layout feature in the layout design comprising geometric parameters is extracted. Parasitic values associated with the layout feature are then computed based on the geometric information and one or more executable files selected in a plurality of executable files which are a compact representation of process calibration data.

Abstract: Methods and apparatus are disclosed for symbolic methods using algebraic geometry (e.g., based on a Gröbner basis of tangent space polynomials of parametric curves). For example, the design, optimization and verification of silicon photonic wave guides using parametric polynomials and/or Gröbner basis functions can be used to perform envelope generation, rectification, manufacturability checking, singularity detection, reticle and etch processing model generation, tapering loss minimization, and bend loss minimization. In one example, a method of analyzing a layout to be manufactured using a photolithographic process includes producing an envelope of a curve representing a layout object based at least in part on a Gröbner basis and performing one or more analysis operations for the envelope to perform verification and manufacturability checks.

Abstract: Aspects of the disclosed technology relate to techniques of parasitic extraction. A signature for a set of geometric elements of a layout design is computed based on contour-related information. The set of geometric elements corresponds to a net of connected equipotential interconnects of a circuit design. Based on comparing the signature with signatures for sets of geometric elements that have computed parasitic element values, parasitic element values for the set of geometric elements are determined.

Abstract: Aspects of the disclosed technology relate to techniques of parasitic extraction using compact representation of process calibration data. Geometric information of a layout feature in the layout design comprising geometric parameters is extracted. Parasitic values associated with the layout feature are then computed based on the geometric information and one or more executable files selected in a plurality of executable files which are a compact representation of process calibration data.

Abstract: Aspects of the disclosed technology relate to techniques of parasitic extraction. A signature for a set of geometric elements of a layout design is computed based on contour-related information. The set of geometric elements corresponds to a net of connected equipotential interconnects of a circuit design. Based on comparing the signature with signatures for sets of geometric elements that have computed parasitic element values, parasitic element values for the set of geometric elements are determined.

Abstract: This application discloses a computing system to pre-process a physical or geometric layout of a circuit design to determine various attributes of the nets, such as a location and a total capacitance for each net in the geometric layout. The computing system can order extraction of the nets from the geometric layout of the circuit design with a space filling curve based, at least in part, on the locations of the nets in the geometric layout of the circuit design and any coupling capacitance between the nets in the geometric layout of the circuit design. The computing system can selectively decouple nets with a coupling capacitance based, at least in part, on the total capacitance for the nets associated with the coupling capacitance. The computing system can generate an electrical representation for each of the extracted nets and write them to a netlist for the circuit design.

Abstract: Methods and apparatus are disclosed for symbolic methods using algebraic geometry (e.g., based on a Gröbner basis of tangent space polynomials of parametric curves). For example, the design, optimization and verification of silicon photonic wave guides using parametric polynomials and/or Gröbner basis functions can be used to perform envelope generation, rectification, manufacturability checking, singularity detection, reticle and etch processing model generation, tapering loss minimization, and bend loss minimization. In one example, a method of analyzing a layout to be manufactured using a photolithographic process includes producing an envelope of a curve representing a layout object based at least in part on a Gröbner basis and performing one or more analysis operations for the envelope to perform verification and manufacturability checks.

Abstract: Methods and apparatus are disclosed for symbolic methods using algebraic geometry (e.g., based on a Gröbner basis of tangent space polynomials of parametric curves). For example, the design, optimization and verification of silicon photonic wave guides using parametric polynomials and/or Gröbner basis functions can be used to perform envelope generation, rectification, manufacturability, singularity detection, reticle and etch processing model generation, tapering loss minimization, and bend loss minimization. In one example, a method of analyzing a layout to be manufactured using a photolithographic process includes producing an envelope of a curve representing a layout object based at least in part on a Gröbner basis and performing one or more analysis operations for the envelope to perform verification and manufacturability checks.

Abstract: This application discloses a computing system to pre-process a physical or geometric layout of a circuit design to determine various attributes of the nets, such as a location and a total capacitance for each net in the geometric layout. The computing system can order extraction of the nets from the geometric layout of the circuit design with a space filling curve based, at least in part, on the locations of the nets in the geometric layout of the circuit design and any coupling capacitance between the nets in the geometric layout of the circuit design. The computing system can selectively decouple nets with a coupling capacitance based, at least in part, on the total capacitance for the nets associated with the coupling capacitance. The computing system can generate an electrical representation for each of the extracted nets and write them to a netlist for the circuit design.

Abstract: Contour-related information for geometric elements in layout design data is obtained. Relevant portions of the contour-related information are provided to a canonical hash function, from which a canonical signature for the layout design data is generated.

Abstract: Contour-related information for geometric elements in layout design data is obtained. Relevant portions of the contour-related information are provided to a canonical hash function, from which a canonical signature for the layout design data is generated.

Abstract: When a designer designates one or more errors identified in layout design data as false errors, waiver geometric elements corresponding to the designated false errors are created and added to the design. The waiver geometric element may be associated with a verification rule that generated its corresponding false error. When the design is subsequently analyzed using those verification rules in another verification rule check process, the waiver geometric elements are examined, and used to mask those errors associated with a waiver geometric element that would otherwise be displayed to the designer.

Abstract: When a designer designates one or more errors identified in layout design data as false errors, waiver geometric elements corresponding to the designated false errors are created and added to the design. The waiver geometric element may be associated with a verification rule that generated its corresponding false error. When the design is subsequently analyzed using those verification rules in another verification rule check process, the waiver geometric elements are examined, and used to mask those errors associated with a waiver geometric element that would otherwise be displayed to the designer.