Patents by Inventor Sandeep Krishna Thirumala
Sandeep Krishna Thirumala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11782830Abstract: This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.Type: GrantFiled: December 20, 2021Date of Patent: October 10, 2023Assignee: Micron Technologies, Inc.Inventors: Amitava Majumdar, Sandeep Krishna Thirumala, Lingming Yang, Karthik Sarpatwari, Nevil N. Gajera
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Patent number: 11775431Abstract: This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.Type: GrantFiled: December 20, 2021Date of Patent: October 3, 2023Assignee: Micron Technologies, Inc.Inventors: Amitava Majumdar, Sandeep Krishna Thirumala, Lingming Yang, Karthik Sarpatwari, Nevil N. Gajera
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Publication number: 20230236982Abstract: Systems, apparatuses, and methods related to a memory controller for performing row access tracking to mitigate row hammer attacks. A memory controller comprises a dual cache system including a direct mapped cache and a victim cache. The direct mapped cache functions as the main cache while a fully associative victim cache is used to reduce hammer attacks to targeted rows. The direct mapped cache performs an aliasing operation to map at least a portion of data stored in a memory device to the direct mapped cache. The direct mapped cache also uses a plurality of counters operatively coupled to the direct mapped cache to track and monitor the number of activations of the data stored in the direct mapped cache. The memory controller proactively refreshes all adjacent rows in the memory device when the respective counter of the direct mapped cache exceeds a predetermined threshold.Type: ApplicationFiled: June 17, 2022Publication date: July 27, 2023Applicant: Micron Technology, Inc.Inventor: Sandeep Krishna Thirumala
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Publication number: 20230236931Abstract: Provided is a memory system comprising a plurality of memory channels each having a parity bit, a redundant array of independent devices (RAID) parity channel, and a controller of the memory system. The controller is configured to receive a block of data for storage in the memory channels and determine at least one of (i) when a data traffic demand on the memory channels is high and (ii) when a data traffic demand on the memory channels is low. Upon determining the data traffic demand is low, writing the block of data for storage in the memory channels and concurrently updating the parity bits and the RAID parity channel for the stored block of data. Upon determining the data traffic demand is high, only writing the data for storage in the memory channels.Type: ApplicationFiled: August 24, 2022Publication date: July 27, 2023Applicant: Micron Technology, Inc.Inventors: Lingming Yang, Amitava Majumdar, Sandeep Krishna Thirumala, Nevil Gajera
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Publication number: 20230236934Abstract: Provided is a memory system including a plurality of memory submodules and a controller. Each submodule comprises a plurality of memory channels, each channel having a parity bit and a redundant array of independent devices (RAID) parity channel. The controller is configured to receive a block of data for storage in the plurality of memory submodules and determine whether a level of data traffic demand for a first of the plurality of submodules is high or low. When the data traffic demand is low, (i) writing a portion of the block of data in the first of the plurality of submodules and (ii) concurrently updating the parity bit and the RAID parity channel associated with the block of data. When the data traffic demand is high, (i) only writing the portion of the block of data in the first of the plurality of submodules and (ii) deferring updating of the parity bits and the RAID parity channel associated with the block of data.Type: ApplicationFiled: August 24, 2022Publication date: July 27, 2023Applicant: Micron Technology, Inc.Inventors: Lingming Yang, Amitava Majumdar, Sandeep Krishna Thirumala, Nevil Gajera
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Publication number: 20230236933Abstract: Systems, apparatuses, and methods can include a multi-stage cache for providing high reliability, availability, and serviceability (RAS). The multi-stage cache memory comprises a shadow DRAM, which is provided on a volatile main memory module, coupled to a memory controller cache, which is provided on a memory controller. During a first write operation, the memory controller writes data with a strong error correcting code (ECC) from the memory controller cache to the shadow DRAM without writing a RAID (Redundant Arrays of Inexpensive Disks) parity data. During a second write operation, the memory controller writes the data with the strong ECC and writes the RAID parity data from the shadow DRAM to a memory device provided on the volatile main memory module.Type: ApplicationFiled: January 18, 2023Publication date: July 27, 2023Applicant: Micron Technology, Inc.Inventors: Sandeep Krishna THIRUMALA, Lingming YANG, Amitava MAJUMDAR, Nevil GAJERA
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Publication number: 20230238049Abstract: Provided is a memory system including a memory module bank comprising a plurality of memory cell arrays, each memory cell array comprising a plurality of memory cells arranged in wordlines and bitlines and a memory controller configured to receive from a central processing unit (CPU) a data byte to be stored in a wordline of the memory module bank. Also included is a logical-to-physical address mapping block (L2P AMB) configured to map a logical bitline address of the data byte to a physical bitline address of a first memory cell array of the plurality of memory cell arrays, wherein a plurality of logical bitline addresses of the data byte are shuffled to different physical bitline memory addresses of the first memory cell array. Each respective memory cell array of the plurality stores a respective bit value, corresponding to a common logical bitline address, to a different respective physical bitline in each different respective memory cell array of the plurality.Type: ApplicationFiled: June 20, 2022Publication date: July 27, 2023Applicant: Micron Technology, Inc.Inventors: Sandeep Krishna Thirumala, Amitava Majumdar, Lingming Yang, Nevil Gajera
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Patent number: 11688445Abstract: A memory cell is disclosed which includes a semiconductor layer, a first electrode coupled to the semiconductor layer, a second electrode coupled to the semiconductor layer, wherein the first and second electrodes are separated from one another along a first axis and wherein the semiconductor layer extends beyond the first axis along a second axis substantially perpendicular to the first axis, thereby forming a first wing, a third electrode separated from the semiconductor layer by an insulating layer, a first magnetic tunnel junction (MTJ) disposed on the first wing, and a first read electrode coupled to the first MTJ.Type: GrantFiled: January 30, 2022Date of Patent: June 27, 2023Assignee: Purdue Research FoundationInventors: Sandeep Krishna Thirumala, Sumeet Kumar Gupta, Yi-Tse Hung, Zhihong Chen
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Publication number: 20230195623Abstract: This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.Type: ApplicationFiled: December 20, 2021Publication date: June 22, 2023Applicant: Micron Technology, Inc.Inventors: Amitava Majumdar, Sandeep Krishna Thirumala, Lingming Yang, Karthik Sarpatwari, Nevil N. Gajera
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Publication number: 20230195624Abstract: This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.Type: ApplicationFiled: December 20, 2021Publication date: June 22, 2023Applicant: Micron Technology, Inc.Inventors: Amitava Majumdar, Sandeep Krishna Thirumala, Lingming Yang, Karthik Sarpatwari, Nevil N. Gajera
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Publication number: 20220157359Abstract: A memory cell is disclosed which includes a semiconductor layer, a first electrode coupled to the semiconductor layer, a second electrode coupled to the semiconductor layer, wherein the first and second electrodes are separated from one another along a first axis and wherein the semiconductor layer extends beyond the first axis along a second axis substantially perpendicular to the first axis, thereby forming a first wing, a third electrode separated from the semiconductor layer by an insulating layer, a first magnetic tunnel junction (MTJ) disposed on the first wing, and a first read electrode coupled to the first MTJ.Type: ApplicationFiled: January 30, 2022Publication date: May 19, 2022Applicant: Purdue Research FoundationInventors: Sandeep Krishna Thirumala, Sumeet Kumar Gupta, Yi-Tse Hung, Zhihong Chen
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Patent number: 11250896Abstract: A memory cell is disclosed which includes a conductive layer, an insulating layer disposed atop the conducting layer, a semiconductor layer disposed atop the insulating layer, a first electrode coupled to the semiconductor layer, a second electrode coupled to the semiconductor layer, wherein the first and second electrodes are separated from one another and wherein the semiconductor layer extends beyond the first and second electrodes forming a first wing, a third electrode coupled to the conductive layer, a first magnetic tunnel junction (MTJ) disposed on the first wing, and a first read electrode coupled to the first MTJ.Type: GrantFiled: June 23, 2020Date of Patent: February 15, 2022Assignee: Purdue Research FoundationInventors: Sandeep Krishna Thirumala, Sumeet Kumar Gupta, Yi-Tse Hung, Zhihong Chen
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Publication number: 20200402560Abstract: A memory cell is disclosed which includes a conductive layer, an insulating layer disposed atop the conducting layer, a semiconductor layer disposed atop the insulating layer, a first electrode coupled to the semiconductor layer, a second electrode coupled to the semiconductor layer, wherein the first and second electrodes are separated from one another and wherein the semiconductor layer extends beyond the first and second electrodes forming a first wing, a third electrode coupled to the conductive layer, a first magnetic tunnel junction (MTJ) disposed on the first wing, and a first read electrode coupled to the first MTJ.Type: ApplicationFiled: June 23, 2020Publication date: December 24, 2020Applicant: Purdue Research FoundationInventors: Sandeep Krishna Thirumala, Sumeet Kumar Gupta, Yi-Tse Hung, Zhihong Chen