Patents by Inventor Sandeep Krishnegowda
Sandeep Krishnegowda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250077677Abstract: Systems, methods, and devices securely boot processors and nonvolatile memories. Methods include implementing, using a controller of a secured nonvolatile memory, a validation operation on a first portion of code stored in a first secured storage region of the secured nonvolatile memory, the validation operation comprising computing a validation value. Methods also include retrieving a second portion of code from a second secured storage region, the second portion of code comprising a pre-computed validation value, the first and second portion of code being associated with booting a processor, and implementing a comparison operation of the validation value and the pre-computed validation value. Methods further include generating, using the controller, a signal based on a result of the comparison operation, the signal being provided to the processor via an interface of the secured nonvolatile memory, and the signal enabling booting of the processor in response to a matching comparison operation.Type: ApplicationFiled: March 6, 2024Publication date: March 6, 2025Applicant: Infineon Technologies LLCInventors: Sandeep Krishnegowda, Zhi FENG
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Patent number: 11954206Abstract: Systems, methods, and devices securely boot processors and nonvolatile memories. Methods include implementing, using a controller of a secured nonvolatile memory, a validation operation on a first portion of code stored in a first secured storage region of the secured nonvolatile memory, the validation operation comprising computing a validation value. Methods also include retrieving a second portion of code from a second secured storage region, the second portion of code comprising a pre-computed validation value, the first and second portion of code being associated with booting a processor, and implementing a comparison operation of the validation value and the pre-computed validation value. Methods further include generating, using the controller, a signal based on a result of the comparison operation, the signal being provided to the processor via an interface of the secured nonvolatile memory, and the signal enabling booting of the processor in response to a matching comparison operation.Type: GrantFiled: June 25, 2021Date of Patent: April 9, 2024Assignee: Infineon Technologies LLCInventors: Sandeep Krishnegowda, Zhi Feng
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Publication number: 20220284105Abstract: Systems, methods, and devices securely boot processors and nonvolatile memories. Methods include implementing, using a controller of a secured nonvolatile memory, a validation operation on a first portion of code stored in a first secured storage region of the secured nonvolatile memory, the validation operation comprising computing a validation value. Methods also include retrieving a second portion of code from a second secured storage region, the second portion of code comprising a pre-computed validation value, the first and second portion of code being associated with booting a processor, and implementing a comparison operation of the validation value and the pre-computed validation value. Methods further include generating, using the controller, a signal based on a result of the comparison operation, the signal being provided to the processor via an interface of the secured nonvolatile memory, and the signal enabling booting of the processor in response to a matching comparison operation.Type: ApplicationFiled: June 25, 2021Publication date: September 8, 2022Applicant: Infineon Technologies LLCInventors: Sandeep Krishnegowda, Zhi Feng
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Patent number: 11411747Abstract: A device can include a plurality of regions, each region including a plurality of nonvolatile memory cells; a permission store configured to store a set of permission values, including at least one permission value for each region in a nonvolatile fashion; and access control circuits configured to control access to each region according to the permission value for the region, including one or more of requiring authentication to access the region, encrypting data read from the region, and decrypting data for storage in the region. Related methods and systems are also disclosed.Type: GrantFiled: December 14, 2020Date of Patent: August 9, 2022Assignee: Infineon Technologies LLCInventors: Hans Van Antwerpen, Clifford Zitlaw, Stephan Rosner, Yoav Yogev, Sandeep Krishnegowda, Steven Wilson
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Patent number: 11316687Abstract: Disclosed are apparatus and methods for programming a plurality of nonvolatile memory (NVM) devices. Each NVM device self-generates and stores a unique encryption key. Each NVM device concurrently receives an image from a multiple-device programming system to which all the NVM devices are communicatively coupled. Each NVM device encrypts the received image using such NVM device's unique encryption key to produce a unique encrypted image for each NVM device. Each NVM device stores its unique encrypted image within a nonvolatile memory of such NVM device. The unique encryption key can then be securely transferred to a host device for decrypting the image accessed from one of the NVM devices.Type: GrantFiled: December 13, 2019Date of Patent: April 26, 2022Assignee: Cypress Semiconductor CorporationInventors: Clifford Zitlaw, Markus Unseld, Sandeep Krishnegowda, Daisuke Nakata, Shinsuke Okada, Stephan Rosner
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Patent number: 11082449Abstract: Disclosed are systems and methods for diagnosing the health of a plurality of memory cells in a memory array. Diagnostics are initiated from a remote server via an encrypted channel on the memory device embedded in an end-use system. The memory device includes a plurality of memory cells in a memory array. At the remote server, encrypted diagnostics data is received in response to execution of a diagnostics program by the memory device on the plurality of memory cells. The diagnostics data pertains to the health of the memory cells. The encrypted diagnostics data is decrypted into decrypted diagnostics data and the decrypted diagnostics data is analyzed to determine the health of the memory cells. Failure mitigation is performed for the memory device if the analyzing indicates unhealthy memory cells.Type: GrantFiled: March 25, 2020Date of Patent: August 3, 2021Assignee: Cypress Semiconductor CorporationInventors: Wen-Ching Chou, Sandeep Krishnegowda, Qamrul Hasan
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Publication number: 20210234708Abstract: A device can include a plurality of regions, each region including a plurality of nonvolatile memory cells; a permission store configured to store a set of permission values, including at least one permission value for each region in a nonvolatile fashion; and access control circuits configured to control access to each region according to the permission value for the region, including one or more of requiring authentication to access the region, encrypting data read from the region, and decrypting data for storage in the region. Related methods and systems are also disclosed.Type: ApplicationFiled: December 14, 2020Publication date: July 29, 2021Applicant: Cypress Semiconductor CorporationInventors: Hans Van Antwerpen, Clifford Zitlaw, Stephan Rosner, Yoav Yogev, Sandeep Krishnegowda, Steven Wilson
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Publication number: 20210126946Abstract: Disclosed are systems and methods for diagnosing the health of a plurality of memory cells in a memory array. Diagnostics are initiated from a remote server via an encrypted channel on the memory device embedded in an end-use system. The memory device includes a plurality of memory cells in a memory array. At the remote server, encrypted diagnostics data is received in response to execution of a diagnostics program by the memory device on the plurality of memory cells. The diagnostics data pertains to the health of the memory cells. The encrypted diagnostics data is decrypted into decrypted diagnostics data and the decrypted diagnostics data is analyzed to determine the health of the memory cells. Failure mitigation is performed for the memory device if the analyzing indicates unhealthy memory cells.Type: ApplicationFiled: March 25, 2020Publication date: April 29, 2021Applicant: Cypress Semiconductor CorporationInventors: Wen-Ching Chou, Sandeep Krishnegowda, Qamrul Hasan
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Patent number: 10868679Abstract: A device can include a plurality of regions, each region including a plurality of nonvolatile memory cells: a permission store configured to store a set of permission values, including at least one permission value for each region in a nonvolatile fashion; and access control circuits configured to control access to each region according to the permission value for the region, including one or more of requiring authentication to access the region, encrypting data read from the region, and decrypting data for storage in the region. Related methods and systems are also disclosed.Type: GrantFiled: March 23, 2020Date of Patent: December 15, 2020Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Hans Van Antwerpen, Cliff Zitlaw, Stephan Rosner, Yoav Yogev, Sandeep Krishnegowda, Steven Wilson
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Publication number: 20200287716Abstract: Disclosed are apparatus and methods for programming a plurality of nonvolatile memory (NVM) devices. Each NVM device self-generates and stores a unique encryption key. Each NVM device concurrently receives an image from a multiple-device programming system to which all the NVM devices are communicatively coupled. Each NVM device encrypts the received image using such NVM device's unique encryption key to produce a unique encrypted image for each NVM device. Each NVM device stores its unique encrypted image within a nonvolatile memory of such NVM device. The unique encryption key can then be securely transferred to a host device for decrypting the image accessed from one of the NVM devices.Type: ApplicationFiled: December 13, 2019Publication date: September 10, 2020Applicant: Cypress Semiconductor CorporationInventors: Clifford Zitlaw, Markus Unseld, Sandeep Krishnegowda, Daisuke Nakata, Shinsuke Okada, Stephan Rosner
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Patent number: 8254200Abstract: An integrated circuit (IC) including a controller integrally formed on a shared die with the IC and method of operating the same to compensate for process and environmental variations in the IC are provided. In one embodiment the IC is comprised of device and sub-circuits, and the method includes: receiving in the IC electrical power and information on at least one of one or more operational parameters of the IC; and adjusting one or more operating characteristics of at least one of the devices and sub-circuits in the IC based on the received information using a controller integrally formed on a shared die with the IC. Other embodiments are also disclosed.Type: GrantFiled: September 10, 2010Date of Patent: August 28, 2012Inventors: Sherif Eid, Morgan Andrew Whately, Sandeep Krishnegowda
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Publication number: 20110063937Abstract: An integrated circuit (IC) including a controller integrally formed on a shared die with the IC and method of operating the same to compensate for process and environmental variations in the IC are provided. In one embodiment the IC is comprised of device and sub-circuits, and the method includes: receiving in the IC electrical power and information on at least one of one or more operational parameters of the IC; and adjusting one or more operating characteristics of at least one of the devices and sub-circuits in the IC based on the received information using a controller integrally formed on a shared die with the IC. Other embodiments are also disclosed.Type: ApplicationFiled: September 10, 2010Publication date: March 17, 2011Inventors: Sherif Eid, Morgan Andrew Whately, Sandeep Krishnegowda