Patents by Inventor Sandeep Kumar Gupta

Sandeep Kumar Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12175265
    Abstract: Systems and methods are described herein for novel uses and/or improvements for predicting, using machine learning models, a process for a user based on function execution. An indication of completion of a predetermined application function associated with a user may be detected and a plurality of stored parameters associated with the user may be identified. The predetermined application function and the parameters may be input into a machine learning model to determine/obtain a process prediction for the user. The process may include a number of functions that may be sent to a user device for execution.
    Type: Grant
    Filed: March 29, 2024
    Date of Patent: December 24, 2024
    Assignee: Citibank, N.A.
    Inventors: Philip Cody Keister, Vaibhav Kumar Gupta, Sandeep Yellambhotla, Geeta Priyanka Janapareddy, Sharika Kanakam, George Higa, Melissa Mathews, Joelle Bove, Aditya Thipireddy
  • Publication number: 20240356636
    Abstract: Aspects of the subject disclosure may include, for example, a node in a fiber optic network, the node comprising a processing system comprising a processor and executable instructions that, when executed by the processing system, facilitate performance of operations, including receiving an automatic or manual trigger; checking nodes in a current working route for a failure responsive to receiving the automatic or manual trigger; raising an alarm responsive to detecting the failure; and performing operations associated with the automatic or manual trigger responsive to not detecting the failure. Other embodiments are disclosed.
    Type: Application
    Filed: June 1, 2023
    Publication date: October 24, 2024
    Applicant: CIENA CORPORATION
    Inventors: Manish Aggarwal, Sandeep Kumar Gupta, Vikas Chander
  • Patent number: 12046601
    Abstract: Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal. For an embodiment, the Vss terminal of each of the devices in the first majority of the devices at location (i,j), is connected to the Vdd terminal of the device at location (i?1,j), wherein the potential of the Vss terminal of the each device at any location (1,j+1) is higher than the potential of the Vss terminal for another device at location (1,j) by a voltage Xj, for j=1:M?1, wherein a sum of all Xj voltages for j=1:(M?1) is greater than 0.25*VDD.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: July 23, 2024
    Assignee: ZetaGig Inc.
    Inventor: Sandeep Kumar Gupta
  • Patent number: 12021029
    Abstract: Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal, at least a plurality of the devices further including at least one other V_Terz terminal. For an embodiment, the Vss terminal of the device at location (i,j), for i=2:N, j=1:M, is connected to the Vdd terminal of the device at location (i?1,j) resulting in a voltage between the Vdd and Vss terminals of at least a majority of the devices in the array to be a substantially same voltage VDD, wherein the potential of the Vss terminal of the each device at any location (i,j+1) is generated to be higher than the potential of the Vss terminal for another device at location (i,j) by a voltage Xj, for i=1:N, j=1:M?1.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: June 25, 2024
    Assignee: ZetaGig Inc.
    Inventor: Sandeep Kumar Gupta
  • Patent number: 12021526
    Abstract: Apparatuses, and methods, for digital cells power reduction are disclosed. For an embodiment, a first plurality of digital logic cells are directly connected to a Vdd terminal and a Vss terminal that have a potential difference of VDD, a second plurality of digital logic cells being directly connected to a Vdd_R terminal and a Vss_R terminal, wherein a potential difference between the Vdd_R terminal and the Vss terminal is (VDD?X1), and a potential difference between the Vss_R terminal and the Vss terminal is X2, wherein at least one digital logic cell has at least one of (a) an input connected to an output of at least one digital logic cell of the second plurality, or (b) an output connected to an input of at least one digital logic cell of the second plurality. Vdd, Vdd_R and Vss_R terminal voltages can be generated by an array of devices.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: June 25, 2024
    Assignee: Zeta Gig Inc.
    Inventor: Sandeep Kumar Gupta
  • Publication number: 20240154614
    Abstract: Apparatuses, and methods, for digital cells power reduction are disclosed. For an embodiment, a first plurality of digital logic cells are directly connected to a Vdd terminal and a Vss terminal that have a potential difference of VDD, a second plurality of digital logic cells being directly connected to a Vdd_R terminal and a Vss_R terminal, wherein a potential difference between the Vdd_R terminal and the Vss terminal is (VDD?X1), and a potential difference between the Vss_R terminal and the Vss terminal is X2, wherein at least one digital logic cell has at least one of (a) an input directly connected to an output of at least one digital logic cell of the second plurality, or (b) an output directly connected to an input of at least one digital logic cell of the second plurality. Vdd, Vdd_R and Vss_R terminal voltages can be generated by an array of devices.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 9, 2024
    Applicant: ZetaGig Inc.
    Inventor: Sandeep Kumar Gupta
  • Patent number: 11967984
    Abstract: Systems and methods for performing a Control Plane Triggered (CPT) Optical Protection Switching (OPS) policy are provided. A method, according to one implementation, includes performing a first route switching procedure for switching routes between an originating node and a terminating node. The first route switching procedure is configured to operate at a first priority level according to an Optical Protection Switching (OPS) policy. The method also includes performing a second route switching procedure for switching routes between the originating node and the terminating node. The second route switching procedure is configured to operate at a second priority level according to a second protection policy, wherein the second priority level is higher than the first priority level. Also, the method includes reverting back to a home path according to the first route switching procedure after one or more faults, defects, or degradations have been cleared from the home path.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: April 23, 2024
    Assignee: Ciena Corporation
    Inventors: Sandeep Kumar Gupta, Vikas Chander, Manish Aggarwal, Parmita Kandiyal
  • Patent number: 11953963
    Abstract: Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal, at least a plurality of the devices further including at least one other V_Terz terminal. For an embodiment, the Vss terminal of the device at location (i,j), for i=2:N, j=1:M, is connected to the Vdd terminal of the device at location (i?1,j) resulting in a voltage between the Vdd and Vss terminals of at least a majority of the devices in the array to be a substantially same voltage VDD, wherein the potential of the Vss terminal of the each device at any location (i,j+1) is generated to be higher than the potential of the Vss terminal for another device at location (i,j) by a voltage Xj, for i=1:N, j=1:M?1.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: April 9, 2024
    Assignee: ZetaGig Inc.
    Inventor: Sandeep Kumar Gupta
  • Publication number: 20230344513
    Abstract: Systems and methods for performing a Control Plane Triggered (CPT) Optical Protection Switching (OPS) policy are provided. A method, according to one implementation, includes performing a first route switching procedure for switching routes between an originating node and a terminating node. The first route switching procedure is configured to operate at a first priority level according to an Optical Protection Switching (OPS) policy. The method also includes performing a second route switching procedure for switching routes between the originating node and the terminating node. The second route switching procedure is configured to operate at a second priority level according to a second protection policy, wherein the second priority level is higher than the first priority level. Also, the method includes reverting back to a home path according to the first route switching procedure after one or more faults, defects, or degradations have been cleared from the home path.
    Type: Application
    Filed: June 8, 2022
    Publication date: October 26, 2023
    Inventors: Sandeep Kumar Gupta, Vikas Chander, Manish Aggarwal, Parmita Kandiyal
  • Publication number: 20230261659
    Abstract: Apparatuses, and methods, for digital cells power reduction are disclosed. For an embodiment, a first plurality of digital logic cells are directly connected to a Vdd terminal and a Vss terminal that have a potential difference of VDD, a second plurality of digital logic cells being directly connected to a Vdd_R terminal and a Vss_R terminal, wherein a potential difference between the Vdd_R terminal and the Vss terminal is (VDD?X1), and a potential difference between the Vss_R terminal and the Vss terminal is X2, wherein at least one digital logic cell has at least one of (a) an input connected to an output of at least one digital logic cell of the second plurality, or (b) an output connected to an input of at least one digital logic cell of the second plurality. Vdd, Vdd_R and Vss_R terminal voltages can be generated by an array of devices.
    Type: Application
    Filed: March 1, 2022
    Publication date: August 17, 2023
    Inventor: Sandeep Kumar Gupta
  • Publication number: 20230261656
    Abstract: Apparatuses, and methods, for digital cells power reduction are disclosed. For an embodiment, a first plurality of digital logic cells are directly connected to a Vdd terminal and a Vss terminal that have a potential difference of VDD, a second plurality of digital logic cells being directly connected to a Vdd_R terminal and a Vss_R terminal, wherein a potential difference between the Vdd_R terminal and the Vss terminal is (VDD?X1), and a potential difference between the Vss_R terminal and the Vss terminal is X2, wherein at least one digital logic cell has at least one of (a) an input directly connected to an output of at least one digital logic cell of the second plurality, or (b) an output directly connected to an input of at least one digital logic cell of the second plurality. Vdd, Vdd_R and Vss_R terminal voltages can be generated by an array of devices.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Inventor: Sandeep Kumar Gupta
  • Publication number: 20230260907
    Abstract: Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal, at least a plurality of the devices further including at least one other V_Terz terminal. For an embodiment, the Vss terminal of the device at location (i,j), for i=2:N, j=1:M, is connected to the Vdd terminal of the device at location (i?1,j) resulting in a voltage between the Vdd and Vss terminals of at least a majority of the devices in the array to be a substantially same voltage VDD, wherein the potential of the Vss terminal of the each device at any location (i,j+1) is generated to be higher than the potential of the Vss terminal for another device at location (i,j) by a voltage Xj, for i=1:N, j=1:M?1.
    Type: Application
    Filed: February 21, 2022
    Publication date: August 17, 2023
    Inventor: Sandeep Kumar Gupta
  • Publication number: 20230261001
    Abstract: Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal. For an embodiment, the Vss terminal of each of the devices in the first majority of the devices at location (i,j), is connected to the Vdd terminal of the device at location (i?1,j), wherein the potential of the Vss terminal of the each device at any location (1,j+1) is higher than the potential of the Vss terminal for another device at location (1,j) by a voltage Xj, for j=1:M?1, wherein a sum of all Xj voltages for j=1:(M?1) is greater than 0.
    Type: Application
    Filed: March 1, 2022
    Publication date: August 17, 2023
    Inventor: Sandeep Kumar Gupta
  • Publication number: 20230259148
    Abstract: Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal, at least a plurality of the devices further including at least one other V_Terz terminal. For an embodiment, the Vss terminal of the device at location (i,j), for i=2:N, j=1:M, is connected to the Vdd terminal of the device at location (i?1,j) resulting in a voltage between the Vdd and Vss terminals of at least a majority of the devices in the array to be a substantially same voltage VDD, wherein the potential of the Vss terminal of the each device at any location (i,j+1) is generated to be higher than the potential of the Vss terminal for another device at location (i,j) by a voltage Xj, for i=1:N, j=1:M?1.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Inventor: Sandeep Kumar Gupta
  • Patent number: 11528078
    Abstract: Systems and methods for managing a list or restoration paths are provided. A method, according to one implementation, includes obtaining a list of restoration paths used for restoring transmission in a network when a home path between an originating node and a termination node is unavailable. The restoration paths are listed in a specific order based on ongoing transmission costs, where the ongoing transmission cost for each restoration path is based on characteristics associated with transmitting signals along the respective restoration path. The method also includes the step of reordering the restoration paths in the list based on restoration costs and the ongoing transmission costs. The restoration cost for each restoration path is based on a procedure for switching from the home path to the respective restoration path.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: December 13, 2022
    Assignee: Ciena Corporation
    Inventors: Vikas Chander, Manish Aggarwal, Sandeep Kumar Gupta
  • Publication number: 20220385357
    Abstract: Systems and methods for managing a list or restoration paths are provided. A method, according to one implementation, includes obtaining a list of restoration paths used for restoring transmission in a network when a home path between an originating node and a termination node is unavailable. The restoration paths are listed in a specific order based on ongoing transmission costs, where the ongoing transmission cost for each restoration path is based on characteristics associated with transmitting signals along the respective restoration path. The method also includes the step of reordering the restoration paths in the list based on restoration costs and the ongoing transmission costs. The restoration cost for each restoration path is based on a procedure for switching from the home path to the respective restoration path.
    Type: Application
    Filed: July 9, 2021
    Publication date: December 1, 2022
    Inventors: Vikas Chander, Manish Aggarwal, Sandeep Kumar Gupta
  • Patent number: 11509978
    Abstract: Systems and methods for utilizing backup paths to restore service in a network are provided. A method, according to one implementation, includes obtaining a route list as defined by a user, the route list including a plurality of explicitly-configured backup routes for restoring service between a source node and a destination node in a network when a working route is unavailable. The method also includes receiving input designating one or more of the explicitly-configured backup routes as one or more last-resort routes. In response to determining that the working route is unavailable and that the plurality of explicitly-configured backup routes, excluding the one or more last-resort routes, are unavailable, the method includes automatically computing one or more implicitly-computed backup routes.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: November 22, 2022
    Assignee: Ciena Corporation
    Inventors: Manish Aggarwal, Sandeep Kumar Gupta, Vikas Chander, Rashmi Kathuria
  • Patent number: 10593074
    Abstract: Responsive to receiving an indication of a geographical area, one or more constituent areas associated with the geographical area are identified. Boundary data corresponding to the constituent areas is accessed. The boundary data for each constituent area comprises a plurality of geographical location points defining line segments that define the boundary of the corresponding constituent area. Unique portions of line segments are identified. A unique portion of a line segment is a portion of a line segment defined in the boundary data of one and only one of the constituent areas. The geographical area boundary layer is defined. The geographical boundary layer comprises a set of line segments consisting of the unique portions of line segments. A geographical map is provided for display via a user interface. The geographical map comprises a plurality of layers. The plurality of layers comprise one or more map layer sand the geographical area boundary layer.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: March 17, 2020
    Assignee: Liberty Mutual Insurance Company
    Inventors: Benjamin Friedman, Sandeep Kumar Gupta, Vishrut Prakash Srivastava, Jason Lee Kelly, Brenton John Sellati, Christian Alexander Maas, Erin Breslin, Jon Ringer
  • Patent number: 9575752
    Abstract: A method and system is described for managing the development of software source code, and in addition, collecting useful metrics about the development process. A first source code is provided in a desired state. The desired state may be the requirement that the source code can be built or the desired state may be the requirement that the source code can be built and pass one or more tests. A second source code is then received. The second source may be a modified copy of the source code. It is then determined whether the second source code is in the desired state, and the first source code is updated using the second source code in response to the second source code being in the desired state. Metrics that may be collected include: the name of a task, time to complete the task, line of code involved, etc.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: February 21, 2017
    Inventors: Lawrence Taylor Waugh, Sandeep Kumar Gupta
  • Publication number: 20120284694
    Abstract: A method and system is described for managing the development of software source code, and in addition, collecting useful metrics about the development process. A first source code is provided in a desired state. The desired state may be the requirement that the source code can be built or the desired state may be the requirement that the source code can be built and pass one or more tests. A second source code is then received. The second source may be a modified copy of the source code. It is then determined whether the second source code is in the desired state, and the first source code is updated using the second source code in response to the second source code being in the desired state. Metrics that may be collected include: the name of a task, time to complete the task, line of code involved, etc.
    Type: Application
    Filed: July 13, 2012
    Publication date: November 8, 2012
    Inventors: Lawrence Taylor Waugh, Sandeep Kumar Gupta