Abstract: A method of determining a distance between a first device and a second device. The method comprises: performing an initial-ranging-operation, by exchanging two multi-frame ranging cycles between the first device and the second device, to calculate a clock ratio and a multi-frame-cycle-ToF. The method further comprises performing a plurality of single-message ranging cycles, wherein each single-message ranging cycle comprises: at a predetermined first-device-cycle-time after an earlier message is sent from the first device to the second device, the first device sending a single-ranging-message to the second device; determining a second-device-cycle-time as the time between the second device receiving the single-ranging-message and the earlier message being received by the second device; determining a current-message-ToF based on: the previous-message-ToF, the first-device-cycle-time, the clock ratio, and the second-device-cycle-time.

Abstract: An ultra-wideband, UWB, receiver module (213) comprising: an antenna for wirelessly receiving UWB signalling from a UWB transmitter module (212) and a processor. The processor is configured to: determine a channel impulse response, CIR, (519) of the wirelessly received UWB signalling, wherein the CIR comprises a plurality of channel taps each having a tap-response-value; identify a predetermined feature (520) in the CIR and an associated channel tap; and based on the channel tap that is associated with the identified feature (520) in the CIR (519), synchronize the UWB receiver module (213) for reception of subsequent UWB signalling.

Abstract: A bias block for providing a bias voltage includes a transistor having a control terminal, a first current terminal and a second current terminal. A voltage level at the control terminal determines a magnitude of current flowing between the first current terminal and the second current terminal. The first current terminal is coupled to a supply voltage via a first impedance and the second current terminal is coupled to a constant reference potential via a second impedance. The second current terminal provides the bias voltage. The bias block further includes a capacitor coupled between the control terminal and the second current terminal of the transistor.

Abstract: An ultra-wideband, UWB, receiver module (213) comprising: an antenna for wirelessly receiving UWB signalling from a UWB transmitter module (212) and a processor. The processor is configured to: determine a channel impulse response, CIR, (519) of the wirelessly received UWB signalling, wherein the CIR comprises a plurality of channel taps each having a tap-response-value; identify a predetermined feature (520) in the CIR and an associated channel tap; and based on the channel tap that is associated with the identified feature (520) in the CIR (519), synchronize the UWB receiver module (213) for reception of subsequent UWB signalling.

Abstract: A method of determining a distance between a first device and a second device. The method comprises: performing an initial-ranging-operation, by exchanging two multi-frame ranging cycles between the first device and the second device, to calculate a clock ratio and a multi-frame-cycle-ToF. The method further comprises performing a plurality of single-message ranging cycles, wherein each single-message ranging cycle comprises: at a predetermined first-device-cycle-time after an earlier message is sent from the first device to the second device, the first device sending a single-ranging-message to the second device; determining a second-device-cycle-time as the time between the second device receiving the single-ranging-message and the earlier message being received by the second device; determining a current-message-ToF based on: the previous-message-ToF, the first-device-cycle-time, the clock ratio, and the second-device-cycle-time.

Abstract: A method for optimizing power of a ranging sequence includes counting at least one cycle of a first clock during a Crystal Oscillator (XO)-mode to generate a first cycle count. A second clock is activated at an end of the XO-mode. The first cycle count is converted into a fractional correction value by multiplying the first cycle count by a ratio of a second period of the second clock divided by a first period of the first clock. A first alignment of the first clock to the second clock is determined at a beginning of the XO-mode. A second alignment of the first clock to the second clock is determined at the end of the XO-mode. An adjusted cycle count is determined by summating the fractional correction value with a summation of the first alignment and the second alignment divided by the first period.

Abstract: A residue block in a stage of a pipeline ADC processing differential signals contains multiple pairs of capacitors. During a hold phase of operation, one capacitor of a pair is connected to a positive reference voltage, and the other capacitor is connected to a negative reference voltage if the input signal exceeds a corresponding threshold voltage. When the input signal does not exceed the corresponding threshold voltage, both capacitors of the pair are connected either to the positive or the negative reference voltage. As a result, the need for a common mode reference voltage may be eliminated, and the residue block can be implemented with a smaller area.

Abstract: A residue block in a stage of a pipeline ADC processing differential signals contains multiple pairs of capacitors. During a hold phase of operation, one capacitor of a pair is connected to a positive reference voltage, and the other capacitor is connected to a negative reference voltage if the input signal exceeds a corresponding threshold voltage. When the input signal does not exceed the corresponding threshold voltage, both capacitors of the pair are connected either to the positive or the negative reference voltage. As a result, the need for a common mode reference voltage may be eliminated, and the residue block can be implemented with a smaller area.

Abstract: Equal common mode voltage is present at the input terminals of an operational amplifier with amplifies the residue signal in a stage of an ADC in two phases while reducing the noise introduced into the amplified signal. A reference capacitor is coupled between an input terminal of the operational amplifier and a reference voltage in a first phase, and between the input terminal and a the reference voltage but with opposite polarity in the second phase.

Abstract: A switched capacitor environment in which a feedback capacitor of a stage is flipped to be used as a sampling capacitor of the next stage. Due to such use of the feedback capacitor, the noise introduced by the stages is substantially reduced. Such switched capacitors can be used in analog to digital converters (ADC).