Abstract: Systems and methods for decoding are described. A decoder system is configured to retrieve, from the grain array stored within the on-chip memory, noise pixel data associated with at least one reconstructed video pixel. The decoder system is configured to apply noise data to the at least one reconstructed video pixel to generate at least one output video pixel. The noise data is determined based on the noise pixel data.

Abstract: Systems and techniques are provided for processing video data. For example, an apparatus may obtain one or more first sets of collocated motion vector data and one or more second sets of collocated motion vector data, associated with a respective first and second block of video data included in a current frame of video data. The apparatus may project the one or more first sets of collocated motion vector data into a first projected motion field associated with a first buffer and project the one or more second sets of collocated motion vector data into the first projected motion field associated with the first buffer. Based on projecting the one or more first sets and one or more second sets of collocated motion vector data, the apparatus may decode the first block of video data based on the first projected motion field associated with the first buffer.

Abstract: Video decoding systems and techniques are described. A decoder reads first video data from a first block of a video frame. The decoder retrieves neighboring video data from a line buffer. The neighboring video data is from a neighboring block that neighbors the first block in the video frame. The decoder processes the first video data and the retrieved neighboring video data using a constrained directional enhancement filter (CDEF) to generate filtered first video data. The decoder upscales the filtered first video data using an upscaler to generate upscaled filtered first video data. The decoder upscales the retrieved neighboring video data using the upscaler to generate upscaled neighboring video data, for instance after generating the filtered first video data. The decoder processes the upscaled filtered first video data and the upscaled neighboring video data using a loop restoration (LR) filter to generate output video data.

Abstract: Video decoding systems and techniques are described. The decoder applies a deblocking (DB) filter to the plurality of sub-blocks of a block of video data to generate a DB-filtered plurality of sub-blocks. The decoder applies the DB filter to one or more lines (e.g., columns) of pixels in an additional sub-block of the block to generate a DB-filtered portion of the additional sub-block. The one or more lines of pixels in the additional sub-block are filtered without filtering an entirety of the additional sub-block using the DB filter. The additional sub-block is adjacent to at least one of the plurality of sub-blocks. The decoder applies a constrained directional enhancement filter (CDEF) to the DB-filtered plurality of sub-blocks and the DB-filtered portion of the additional sub-block to generate a CDEF-filtered plurality of sub-blocks.

Abstract: Certain aspects of the present disclosure provide techniques for scalably and efficiently converting linear image data into multi-dimensional image data for multimedia applications. In one example, a method for managing image data includes receiving a line of image data in a linear format via a system bus of width T, wherein the image data's native format is a tile format of H lines per tile; forming H subsets of image data from the line of image data in the linear format; writing the H subsets of image data to a memory comprising BN=H banks of BW=T/BN pixel width, wherein each subset of the H subsets is written to a different bank of the BN banks; and outputting the H subsets of image data in the tile format.

Abstract: Certain aspects of the present disclosure provide techniques for scalably and efficiently converting linear image data into multi-dimensional image data for multimedia applications. In one example, a method for managing image data includes receiving a line of image data in a linear format via a system bus of width T, wherein the image data's native format is a tile format of H lines per tile; forming H subsets of image data from the line of image data in the linear format; writing the H subsets of image data to a memory comprising BN=H banks of BW=T/BN pixel width, wherein each subset of the H subsets is written to a different bank of the BN banks; and outputting the H subsets of image data in the tile format.

Abstract: An integrated circuit is disclosed for data retention with data migration. In an example aspect, the integrated circuit includes a logic block, a memory block, and retention control circuitry coupled to the logic and memory blocks. The logic block includes multiple retention-relevant storage devices to store first data and second data. The multiple retention-relevant storage devices include a first group of retention-relevant storage devices to store the first data and a second group of retention-relevant storage devices to store the second data. The memory block maintains memory data in the memory block during a retention operational mode. The retention control circuitry causes the retention-relevant storage devices of the second group to be activated into multiple scan chains and also migrates the second data between the second group and the memory block using the multiple scan chains to accommodate transitions between the retention operational mode and a regular operational mode.

Abstract: A computer-implemented method for generating a circuit design is provided according to certain aspects. The method includes determining a gating efficiency of first gate-enable logic, determining a gating efficiency of second gate-enable logic, and determining one of the first gate-enable logic and the second gate-enable logic having a greater one of the determined gating efficiencies. The method also includes placing the determined one of the first gate-enable logic and the second gate-enable logic in clock gating logic of the circuit design, and placing another one of the first gate-enable logic and the second gate-enable in data gating logic of the circuit design.

Abstract: An integrated circuit is disclosed for data retention with data migration. In an example aspect, the integrated circuit includes a logic block, a memory block, and retention control circuitry coupled to the logic and memory blocks. The logic block includes multiple retention-relevant storage devices to store first data and second data. The multiple retention-relevant storage devices include a first group of retention-relevant storage devices to store the first data and a second group of retention-relevant storage devices to store the second data. The memory block maintains memory data in the memory block during a retention operational mode. The retention control circuitry causes the retention-relevant storage devices of the second group to be activated into multiple scan chains and also migrates the second data between the second group and the memory block using the multiple scan chains to accommodate transitions between the retention operational mode and a regular operational mode.

Abstract: A computer-implemented method for generating a circuit design is provided according to certain aspects. The method includes determining a gating efficiency of first gate-enable logic, determining a gating efficiency of second gate-enable logic, and determining one of the first gate-enable logic and the second gate-enable logic having a greater one of the determined gating efficiencies. The method also includes placing the determined one of the first gate-enable logic and the second gate-enable logic in clock gating logic of the circuit design, and placing another one of the first gate-enable logic and the second gate-enable in data gating logic of the circuit design.