Abstract: A method is disclosed that employs a hierarchical path database generator for accessing internal signal or port names in a design hierarchy of an integrated circuit design. The method comprises the steps of inputting design files into the hierarchical path database generator; and said hierarchical path database generator determining ports and signals in said design files, and storing the names of said ports and signals in a hierarchical database in a logical hierarchical order. The method comprises the further steps of providing a testcase to verify a defined aspect of the integrated circuit design; parsing the testcase to identify all signal and port names therein; and for each of the signal and port names identified in the testcase, inputting said each name into the hierarchical path database generator, and obtaining from that generator a hierarchical path associated with said each signal and port name.

Abstract: A method is disclosed that employs a hierarchical path database generator for accessing internal signal or port names in a design hierarchy of an integrated circuit design. The method comprises the steps of inputting design files into the hierarchical path database generator; and said hierarchical path database generator determining ports and signals in said design files, and storing the names of said ports and signals in a hierarchical database in a logical hierarchical order. The method comprises the further steps of providing a testcase to verify a defined aspect of the integrated circuit design; parsing the testcase to identify all signal and port names therein; and for each of the signal and port names identified in the testcase, inputting said each name into the hierarchical path database generator, and obtaining from that generator a hierarchical path associated with said each signal and port name.