Abstract: A processor-implemented method for a memory storage format to accelerate machine learning (ML) on a computing device is described. The method includes receiving an image in a first layer storage format of a neural network. The method also includes assigning addresses to image pixels of each of three channels of the first layer storage format for accessing the image pixels in a blocked ML storage acceleration format. The method further includes storing the image pixels in the blocked ML storage acceleration format according to the assigned addresses of the image pixels. The method also includes accelerating inference video processing of the image according to the assigned addresses for the image pixels corresponding to the blocked ML storage acceleration format.

Abstract: The present disclosure relates to a memory device comprising a memory array and a periphery circuitry configured to read data from and/or write data to the memory array, wherein the periphery circuitry comprises a programmable circuitry causing the memory device to access data stored in the memory array in accordance with manifest loop instructions. The programmable circuitry comprises a control logic configured to control the operation of the periphery circuitry in accordance with a set of parameters derived from the manifest loop instructions. The present disclosure further relates to a method for controlling the operation of a memory device and to a processing system comprising the memory device.