Abstract: An anonymous non-emergency help system matches capabilities of potential helpers to a requestor's needs. Helpers identify the type of assistance they are willing to provide and then agree to become available anonymously. The helpers are contacted sequentially for assistance based on proximity to the requestor. The nearest helper may choose to respond or decline the request. This anonymous location process occurs sequentially, awaiting a requestor-defined timeout, until one of the identified individuals agrees to fulfill the request or until there are no other proximate individuals that meet the specific request criteria. A call for help is not broadcast, but helpers are chosen based on their disclosed skills/capabilities, attributes, and their proximity to the requestor. The attributes are related to at least one of speed and trajectory relative to the requestor, time the helper is in a particular location, and altitude difference between the requestor and the helper.

Abstract: Protection is provided against electrical surges resulting from Electrical Over Stress conditions, e.g., when interfacing circuits with powered connections. An EOS shunt is activated for as long as the EOS condition exists. EOS protection using an EOS shunt in accordance with the principles of the present invention remains activated by a voltage threshold trigger as long as necessary. In a disclosed embodiment, an EOS shunt includes a voltage threshold detector that detects a voltage on a power bus with respect to a ground rail exceeding a predetermined amount, e.g., 5 volts in a device powered at 3.3 volts. During the EOS event, a path between power and ground comprising a transistor is turned on.

Abstract: Protection is provided against electrical surges resulting from Electrical Over Stress conditions, e.g., when interfacing circuits with powered connections. An EOS shunt is activated for as long as the EOS condition exists. EOS protection using an EOS shunt in accordance with the principles of the present invention remains activated by a voltage threshold trigger as long as necessary. In a disclosed embodiment, an EOS shunt includes a voltage threshold detector that detects a voltage on a power bus with respect to a ground rail exceeding a predetermined amount, e.g., 5 volts in a device powered at 3.3 volts. During the EOS event, a path between power and ground comprising a transistor is turned on.

Abstract: The invention relates to a voltage reference source used to control an overvoltage tolerant input/output buffer for a mixed voltage bus system. The voltage source comprises a voltage tracking circuit having a first input receiving a variable voltage. and a second input receiving a reference voltage. the voltage tracking circuit being adapted to generate an output voltage in response to the difference between the variable voltage and the reference voltage. wherein where the variable voltage is less than the reference voltage. the output voltage is held at substantially zero volts. When the variable voltage exceeds the reference voltage. the output tracks the voltage at the variable voltage input.

Abstract: The frequency doubling circuit according to the present invention includes first and second pulse generating circuits generating first and second pulse trains based on a periodic input signal. The second pulse train is out of phase with the first pulse train, and a combining circuit combines the first and second pulse trains to generate a periodic output signal having twice the frequency of the periodic input signal. Both the first and second pulse generating circuits include first and second charge storage devices, with the second charge storage device having half the storage capacity of the first charge storage device.

Abstract: The invention relates to a voltage reference source used to control an overvoltage tolerant input/output buffer for a mixed voltage bus system. The voltage source comprises a voltage tracking circuit having a first input receiving a variable voltage, and a second input receiving a reference voltage, the voltage tracking circuit being adapted to generate an output voltage in response to the difference between the variable voltage and the reference voltage, wherein where the variable voltage is less than the reference voltage, the output voltage is held at substantially zero volts. When the variable voltage exceeds the reference voltage, the output tracks the voltage at the variable voltage input.

Abstract: An electrostatic discharge (ESD) protection circuit for an output transistor coupled to an I/O pin of an integrated circuit, including a logic circuit having at least one data input, a tristate enable input, and an tristate output coupled to a gate node of the output transistor wherein the tristate output is placed in a high impedance state in response to the tristate enable input. The ESD protection circuit also includes a tristate enable circuit which drives the tristate enable input according to the presence or absence of an ESD event on the I/O pin. During normal operation, the tristate enable circuit applies a first logic level to the tristate enable input such that the tristate output of the logic circuit is placed in a low impedance state, and during an ESD event on the I/O pin, the tristate enable circuit applies a second logic level to the tristate enable input such that the tristate output of the logic circuit is placed in a high impedance state.

Abstract: The invention relates to a mixed voltage bus system and in particular, interfaces between a number of integrated circuits and a bus where some of the integrated circuits operate at one logic level and others operate at a different logic level. An overvoltage tolerant interface for a semiconductor integrated device particulary useful in such a system may contain a pad, a pull-up transistor coupled to the pad, a voltage supply having an operating voltage, and an isolation switch operative to isolate the pull-up transistor from the voltage supply when a voltage at the pad exceeds the operating voltage of the voltage supply.

Abstract: An output buffer having a reduced-swing output includes a p-channel pullup transistor as the primary pullup device. A biasing circuit is provided so as to bias the gate terminal of the pullup p-channel transistor to a predetermined level. The predetermined level is effective to cause the p-channel pullup transistor to shut off when the output of the buffer reaches a reduced magnitude output level (V.sub.OH). In the disclosed embodiment, the biasing circuit includes an n-channel transistor connected between the gate and drain terminals of the p-channel pullup transistor. The biasing circuit also includes a p-channel transistor having a source terminal connected to V.sub.cc, and a drain terminal connected to the gate of the pullup transistor. When the output of the buffer is desired to be in a logic high state, both of the biasing transistors are "ON.