Abstract: A memory cell array structure includes a memory cell including a memory element and a transistor having a source terminal coupled to a second electrode of the memory element, a bit line coupled to a drain terminal of the transistor and including first and second metal lines extending in a first direction, the second metal line coupled to the first metal line and disposed over the first metal line in a third direction, a word line coupled to a gate terminal of the transistor and including a third metal line that extends in a second direction and is disposed over the second metal line in the third direction, and a source line coupled to a first electrode of the memory element. The first to the third directions are perpendicular to each other. The first and the second metal lines together carry a signal through the bit line.

Abstract: Apparatus and associated methods relate to configuring secure access to a patient's stored health record data, in response to receiving the patient's consent to a health record data access request, and providing the secure access to a specific user at a location and time related to the request. The access request may be received from a provider. The provider may be a doctor. Secure access by a specific user to a discrete health record data field may be configured, granted, or revoked based on patient consent status, permitting the patient selective control over access to their personal health record data. Access encryption parameters distinct from the storage encryption parameters securing the stored health record may be configured to permit specific user access to a specific data field. The access encryption parameters may be revoked by the patient withdrawing consent, permitting the patient to assert ownership control of their health records.

Abstract: Methods and design structures for extraction of transistor channel width are disclosed. Embodiments may include determining effective channel widths of transistors of a plurality of integrated circuits as a function of drawn channel widths of the transistors, and determining a target channel width for a target transistor based on the effective channel widths.

Abstract: Methods and design structures for extraction of transistor channel width are disclosed. Embodiments may include determining effective channel widths of transistors of a plurality of integrated circuits as a function of drawn channel widths of the transistors, and determining a target channel width for a target transistor based on the effective channel widths.

Abstract: Hierarchical layout versus schematic comparison with extraneous device elimination is provided. This includes obtaining a hierarchical layout netlist for a circuit design, the hierarchical layout netlist grouping arrayed devices of the circuit design into blocks repeated at a top level of a hierarchy of the hierarchical layout netlist. A modified hierarchical layout netlist defining active devices and connections thereof to top level pads of the circuit design is generated, in which extraneous devices are selectively removed from the obtained hierarchical layout netlist. The modified hierarchical layout netlist is verified against an input schematic netlist defining active devices of the circuit design and connections thereof to pads of the circuit design.