Abstract: An insulated-gate field-effect transistor (100) provided along an upper surface of a semiconductor body contains a pair of source/drain zones (240 and 242) laterally separated by a channel zone (244). A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. Each source/drain zone includes a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E) laterally continuous with the main portion and extending laterally under the gate electrode. The lateral extensions, which terminate the channel zone along the upper semiconductor surface, are respectively largely defined by a pair of semiconductor dopants of different atomic weights. With the transistor being an asymmetric device, the source/drain zones constitute a source and a drain. The lateral extension of the source is defined with dopant of higher atomic weight than the lateral extension of the drain.

Abstract: An asymmetric insulated-gate field-effect transistor (100) has a source (240) and a drain (242) laterally separated by a channel zone (244) of body material (180) of a semiconductor body. A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. A more heavily doped pocket portion (250) of the body material extends largely along only the source. Each of the source and drain has a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension. These features enable the threshold voltage to be highly stable with operational time.

Abstract: In a gated anti-fuse, an anode is separated from a cathode by an oxide layer and the anode or cathode voltage is controlled by the control gate of a transistor like structure connected to the anode or cathode.

Abstract: Fabrication of an asymmetric field-effect transistor (100) entails defining a gate electrode (262) above, and vertically separated by a gate dielectric layer (260) from, a channel-zone portion (244) of body material of a semiconductor body. Semiconductor dopant is introduced into the body material to define a more heavily doped pocket portion (250) using the gate electrode as a dopant-blocking shield. A spacer (264T) is provided along the gate electrode. The spacer includes (i) a dielectric portion situated along the gate electrode, (ii) a dielectric portion situated along the semiconductor body, and (iii) a filler portion (SC) largely occupying the space between the other two spacer portions. Semiconductor dopant is introduced into the semiconductor body to define a pair of main source/drain portions (240M and 240E) using the gate electrode and the spacer as a dopant-blocking shield. The filler spacer portion is removed to convert the spacer to an L shape (264).

Abstract: An insulated-gate field-effect transistor (100) provided along an upper surface of a semiconductor body contains a pair of source/drain zones (240 and 242) laterally separated by a channel zone (244). A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. Each source/drain zone includes a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E) laterally continuous with the main portion and extending laterally under the gate electrode. The lateral extensions, which terminate the channel zone along the upper semiconductor surface, are respectively largely defined by a pair of semiconductor dopants of different atomic weights. With the transistor being an asymmetric device, the source/drain zones constitute a source and a drain. The lateral extension of the source is then more lightly doped than, and defined with dopant of higher atomic weight, than the lateral extension of the drain.

Abstract: A group of high-performance like-polarity insulated-gate field-effect transistors (100, 108, 112, 116, 120, and 124 or 102, 110, 114, 118, 122, and 126) have selectably different configurations of lateral source/drain extensions, halo pockets, and gate dielectric thicknesses suitable for a semiconductor fabrication platform that provides a wide variety of transistors for analog and/or digital applications. Each transistor has a pair of source/drain zones, a gate dielectric layer, and a gate electrode. Each source/drain zone includes a main portion and a more lightly doped lateral extension. The lateral extension of one of the source/drain zones of one of the transistors is more heavily doped or/and extends less deeply below the upper semiconductor surface than the lateral extension of one of the source/drain zones of another of the transistors.

Abstract: An asymmetric insulated-gate field-effect transistor (100 or 102) has a source (240 or 280) and a drain (242 or 282) laterally separated by a channel zone (244 or 284) of body material (180 or 182) of a semiconductor body. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A more heavily doped pocket portion (250 or 290) of the body material extends largely along only the source. The source has a main source portion (240M or 280M) and a more lightly doped lateral source extension (240E or 280E). The drain has a main portion (242M or 282M) and a more lightly doped lateral drain extension (242E or 282E). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension.

Abstract: A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (100, 102, 112, 114, 124, and 126) utilize empty wells (180, 182, 192, 194, 204, and 206) in achieving desired transistor characteristics. Other IGFETs (108, 110, 116, 118, 120, and 122) utilize filled wells (188, 190, 196, 198, 200, and 202) in achieving desired transistor characteristics.

Abstract: Insulated-gate field-effect transistors (“IGFETs”), both symmetric and asymmetric, suitable for a semiconductor fabrication platform that provides IGFETs for analog and digital applications, including mixed-signal applications, utilize empty-well regions in achieving high performance. A relatively small amount of semiconductor well dopant is near the top of each empty well. Each IGFET (100, 102, 112, 114, 124, or 126) has a pair of source/drain zones laterally separated by a channel zone of body material of the empty well (180, 182, 192, 194, 204, or 206). A gate electrode overlies a gate dielectric layer above the channel zone. Each source/drain zone (240, 242, 280, 282, 520, 522, 550, 552, 720, 722, 752, or 752) has a main portion (240M, 242M, 280M, 282M, 520M, 522M, 550M, 552M, 720M, 722M, 752M, or 752M) and a more lightly doped lateral extension (240E, 242E, 280E, 282E, 520E, 522E, 550E, 552E, 720E, 722E, 752E, or 752E).

Abstract: An asymmetric insulated-gate field effect transistor (100U or 102U) provided along an upper surface of a semiconductor body contains first and second source/drain zones (240 and 242 or 280 and 282) laterally separated by a channel zone (244 or 284) of the transistor's body material. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A pocket portion (250 or 290) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S/D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima (316-1-316-3) at respective locations (PH-1-PH-3) spaced apart from one another. The tailoring is typically implemented so that the vertical dopant profile of the pocket portion is relatively flat near the upper semiconductor surface. As a result, the transistor has reduced leakage current.

Abstract: An extended-drain insulated-gate field-effect transistor (104 or 106) contains first and second source/drain zones 324 and 184B or 364 and 186B) laterally separated by a channel (322 or 362) zone constituted by part of a first well region (184A or 186A). A gate dielectric layer (344 or 384) overlies the channel zone. A gate electrode (346 or 386) overlies the gate dielectric layer above the channel zone. The first source/drain zone is normally the source. The second S/D zone, normally the drain, is constituted with a second well region (184B or 186B). A well-separating portion 186A or 186B/212U) of the semiconductor body extends between the well regions and is more lightly doped than each well region. The configuration of the well regions cause the maximum electric field in the IGFET's portion of the semiconductor body to occur well below the upper semiconductor surface, typically at or close to where the well regions are closest to each other.

Abstract: Method and apparatus for fabricating semiconductor devices, for example, III-V semiconductor devices, having a desired substrate, for example, a silicon substrate. A method for fabricating semiconductor devices includes providing a semiconductor wafer that includes a plurality of semiconductor structures attached to a native substrate formed of a first substrate material, and a host substrate formed of a second substrate material. At least one subset of semiconductor structures of the plurality of semiconductor structures is transferred from the semiconductor wafer to the host substrate to provide a semiconductor device having a substrate formed of the second substrate material.

Abstract: CMOS image sensor having high sensitivity and low crosstalk, particularly at far-red to infrared wavelengths, and a method for fabricating a CMOS image sensor. A CMOS image sensor has a substrate, an epitaxial layer above the substrate, and a plurality of pixels extending into the epitaxial layer for receiving light. The image sensor also includes at least one of a horizontal barrier layer between the substrate and the epitaxial layer for preventing carriers generated in the substrate from moving to the epitaxial layer, and a plurality of lateral barrier layers between adjacent ones of the plurality of pixels for preventing lateral diffusion of electrons in the epitaxial layer.

Abstract: CMOS image sensor having high sensitivity and low crosstalk, particularly at far-red to infrared wavelengths, and a method for fabricating a CMOS image sensor. A CMOS image sensor has a substrate, an epitaxial layer above the substrate, and a plurality of pixels extending into the epitaxial layer for receiving light. The image sensor also includes at least one of a horizontal barrier layer between the substrate and the epitaxial layer for preventing carriers generated in the substrate from moving to the epitaxial layer, and a plurality of lateral barrier layers between adjacent ones of the plurality of pixels for preventing lateral diffusion of electrons in the epitaxial layer.

Abstract: In one aspect, a semiconductor device includes a p-region and an n-region. The p-region includes a first Group IV semiconductor that has a bandgap and is doped with a p-type dopant, and a first region of local crystal modifications inducing localized strain that increases the bandgap of the first Group IV semiconductor and creates a conduction band energy barrier against transport of electrons across the p-region. The n-region includes a second Group IV semiconductor that has a bandgap and is doped with an n-type dopant, and a second region of local crystal modifications inducing localized strain that increases the bandgap of the second Group IV semiconductor and creates a valence band energy barrier against transport of holes across the n-region.

Abstract: In one aspect, a first region that includes a first Group IV semiconductor that has a bandgap and is doped with a first dopant of a first electrical conductivity type is formed. A pattern is created. The pattern controls formation of local crystal modifications in the first Group IV semiconductor in an array. An array of local crystal modifications is formed in the first Group IV semiconductor in accordance with the pattern. The local crystal modifications induce overlapping strain fields that increase the bandgap of the first Group IV semiconductor, create an energy band barrier against transport of minority carriers across the first region. A second region that includes a second Group IV semiconductor that has a bandgap and is doped with a second dopant of a second electrical conductivity type opposite the first conductivity type is formed. Semiconductor devices formed in accordance with this method also are described.

Abstract: A heterojunction bipolar transistor (HBT), including an emitter formed from a first semiconductor material, a base formed from a second semiconductor material, and a grading structure between the emitter and the base is disclosed. The grading structure comprises a semiconductor material containing at least one element not present in the first and second semiconductor materials, where the grading structure has a conduction band energy substantially equal to a conduction band energy of the base at an interface between the base and the grading structure, and where the grading structure has a conduction band energy substantially equal to a conduction band energy of the emitter at an interface between the emitter and the grading structure.

Abstract: A heterojunction bipolar transistor (HBT), including an emitter formed from a first semiconductor material, a base formed from a second semiconductor material, and a grading structure between the emitter and the base is disclosed. The grading structure comprises a semiconductor material containing at least one element not present in the first and second semiconductor materials, where the grading structure has a conduction band energy substantially equal to a conduction band energy of the base at an interface between the base and the grading structure, and where the grading structure has a conduction band energy substantially equal to a conduction band energy of the emitter at an interface between the emitter and the grading structure.

Abstract: Systems and methods of manufacturing etchable heterojunction interfaces and etched heterojunction structures are described. A bottom layer is deposited on a substrate, a transition etch layer is deposited over the bottom layer, and a top layer is deposited over the transition etch layer. The transition etch layer substantially prevents the bottom layer and the top layer from forming a material characterized by a composition substantially different than the bottom layer and a substantially non-selective etchability with respect to the bottom layer. By tailoring the structure of the heterojunction interface to respond to heterojunction etching processes with greater predictability and control, the transition etch layer enhances the robustness of previously unreliable heterojunction device manufacturing processes. The transition etch layer enables one or more vias to be etched down to the top surface of the bottom layer in a reliable and repeatable manner.