Abstract: A processor package module comprises a substrate, one or more compute die mounted to the substrate, and one or more photonic die mounted to the substrate. The photonic die have N optical I/O links to transmit and receive optical I/O signals using a plurality of virtual optical channels, the N optical I/O links corresponding to different types of I/O interfaces excluding power and ground I/O. The substrate is mounted into a socket that support the power and ground I/O and electrical connections between the one or more compute die and the one or more photonic die.

Abstract: Embodiments herein relate to systems, apparatuses, or techniques for using an optical physical layer die within a system-on-a-chip to optically couple with an optical physical layer die on another package to provide high-bandwidth memory access between the system-on-a-chip and the other package. In embodiments, the other package may be a large optically connected memory device that includes a memory controller coupled with an optical physical layer die, where the memory controller is coupled with memory. Other embodiments may be described and/or claimed.

Abstract: The systems and methods described herein are directed to using a plurality of interface elements (e.g., sockets) and/or stud-bump elements embedded into board substrates (e.g., a motherboard) to enable the interchange of variable configuration components (e.g., electronic components, chips, and the like) that are mounted on package substrates having ball grid arrays (BGAs). In some aspects, this interchange can be accomplished while leaving the pre-existing board substrate design and various peripheral system components of the board substrate unchanged.

Abstract: The systems and methods described herein are directed to using a plurality of interface elements (e.g., sockets) and/or stud-bump elements embedded into board substrates (e.g., a motherboard) to enable the interchange of variable configuration components (e.g., electronic components, chips, and the like) that are mounted on package substrates having ball grid arrays (BGAs). In some aspects, this interchange can be accomplished while leaving the pre-existing board substrate design and various peripheral system components of the board substrate unchanged.

Abstract: A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.

Abstract: A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.

Abstract: A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.

Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include coating an interconnect structure disposed on a die with a layer of functionalized nanoparticles, wherein the functionalized nanoparticles are dispersed in a solvent, heating the layer of functionalized nanoparticles to drive off a portion of the solvent, and applying an underfill on the coated interconnect structure.

Abstract: A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.

Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include coating an interconnect structure disposed on a die with a layer of functionalized nanoparticles, wherein the functionalized nanoparticles are dispersed in a solvent, heating the layer of functionalized nanoparticles to drive off a portion of the solvent, and applying an underfill on the coated interconnect structure.

Abstract: Semiconductor packages and methods to fabricate thereof are described. A decoupling assembly is disposed between a package substrate and a circuit board. The decoupling assembly engages in response to a stimulus such that a semiconductor die is de-coupled from a socket and a circuit board. The decoupling assembly engages in response to a stimulus such that a semiconductor die is decoupled from a substrate. A decoupling assembly includes a clamping device, springs, and shape memory alloy rods. The shape memory alloy rods are actuators that generate motion or a pre-programmed shape to apply force when thermally excited. When the thermal excitation or other stimulus is removed, the shape memory alloy rods tend to return to their original shape, thus relieving any load or motion generated.

Abstract: A process for assembling a package for a semiconductor device comprising reducing the stress in an inner dielectric layer during packaging by heating the die and the substrate to a temperature where a solder reflows, dropping to a temperature where a selected epoxy will cure, liquefying the epoxy, adding the liquefied epoxy to the die and substrate, and maintaining the die and substrate at a temperature where the epoxy cures for a selected amount of time.

Abstract: A method, apparatus and system with a semiconductor package including a thermal interface material dam enclosing a volume of thermal interface material.

Abstract: A silicon die having a junction side being attachable to a substrate, a backside surface spaced from the junction side and an underfill control feature to prevent an underfill from settling above said backside surface is disclosed herein.

Abstract: A method for packaging a die includes attaching the die to a substrate using a plurality of pieces of discontinuous die attach material, and injecting a mold compound at the interface between the die and the substrate.

Abstract: A method and apparatus for mounting semiconductor die and integral heat spreader are disclosed. In one embodiment, thermal expansion of the integral heat spreader is restricted by physical constraints during the process of heating interface material that bonds the integral heat spreader and semiconductor die together. In an alternative embodiment, thermal expansion of the integral hat spreader is restricted by applying an external compressive force to the integral heat spreader while heating interface material that bonds the integral heat spreader and semiconductor die together.

Abstract: A method of packaging a die includes reflowing the solder to electrically connect the die to a substrate at a first temperature, cooling the die and substrate to a second temperature, and placing a heated epoxy in contact with the die and the substrate. The method also includes holding the die and substrate at the second temperature for a time sufficient to allow the epoxy to cure, and cooling the die, substrate and epoxy. The second temperature is less than the first temperature. In addition, the die and substrate are not cooled to a temperature significantly below the second temperature until after the heated epoxy is placed in contact with the die and substrate.

Abstract: A method of packaging a die includes reflowing the solder to electrically connect the die to a substrate at a first temperature, cooling the die and substrate to a second temperature, and placing a heated epoxy in contact with the die and the substrate. The method also includes holding the die and substrate at the second temperature for a time sufficient to allow the epoxy to cure, and cooling the die, substrate and epoxy. The second temperature is less than the first temperature. In addition, the die and substrate are not cooled to a temperature significantly below the second temperature until after the heated epoxy is placed in contact with the die and substrate.