Abstract: A sample and hold circuit includes: an input node to which an input voltage signal is configured to be supplied; a first reference voltage node to which a first reference voltage potential is configured to be supplied; a sampling capacitor circuit; a sampling switch transistor circuit connected between the input node and the sampling capacitor circuit; a first common mode switch transistor circuit connected between the sampling capacitor circuit and the first reference voltage node; a signal bootstrap circuit configured to generate a first control voltage based on a clock signal, the first control voltage varying according to a level of the input voltage signal, and configured to control the sampling switch transistor circuit based on the first control voltage; and a static bootstrap circuit configured to generate a second control voltage based on the clock signal, the second control voltage being programmable, and configured to control the first common mode switch transistor circuit based on the second contr

Abstract: Analogue-to-digital converter, ADC, circuitry comprising: successive-approximation circuitry configured in a subconversion operation to draw a charge from a first voltage reference, REF1; compensation circuitry comprising at least one compensation capacitor and configured, in a precharge operation prior to the subconversion operation, to connect the at least one compensation capacitor so that the at least one compensation capacitor stores a compensation charge, and, in the subconversion operation, to connect the at least one compensation capacitor to the first voltage reference so that a charge is injected into the first voltage reference, REF1; and control circuitry, wherein: the successive-approximation circuitry and the compensation circuitry are configured such that one or more parameters defining at least one of said charges are controllable; and the control circuitry is configured to adjust at least one said parameter to adjust an extent to which the charge injected into the first voltage reference, REF

Abstract: A method for compensating a Power Supply Rejection Ratio (PSRR) in an image sensor, the method includes receiving, by processing circuitry, at least one analog signal from an active pixels sensor (APS) array, the at least one analog signal including power supply noise, combining, by the processing circuitry, amplified power supply noise with at least one ramp signal to obtain combined power supply noise, and compensating, by the processing circuitry, the PSRR of the APS array by cancelling the power supply noise of the at least one analog signal using the combined power supply noise.

Abstract: A method for compensating a Power Supply Rejection Ratio (PSRR) in an image sensor, the method includes receiving, by processing circuitry, at least one analog signal from an active pixels sensor (APS) array, the at least one analog signal including power supply noise, combining, by the processing circuitry, amplified power supply noise with at least one ramp signal to obtain combined power supply noise, and compensating, by the processing circuitry, the PSRR of the APS array by cancelling the power supply noise of the at least one analog signal using the combined power supply noise.