Abstract: A voltage reference circuit includes a bandgap circuit and a temperature compensation circuit. The temperature compensation circuit includes a first trim circuit, a second trim circuit, and a resistive digital-to-analog converter. The resistive digital-to-analog converter is coupled to the first trim circuit, the second trim circuit, and the bandgap circuit. The resistive digital-to-analog converter is configured to generate a temperature compensation voltage, and to provide the temperature compensation voltage to the bandgap circuit.

Abstract: A voltage reference circuit includes a bandgap circuit and a temperature compensation circuit. The temperature compensation circuit includes a first trim circuit, a second trim circuit, and a resistive digital-to-analog converter. The resistive digital-to-analog converter is coupled to the first trim circuit, the second trim circuit, and the bandgap circuit. The resistive digital-to-analog converter is configured to generate a temperature compensation voltage, and to provide the temperature compensation voltage to the bandgap circuit.

Abstract: In some examples, a bandgap reference circuit comprises a first bandgap pair having multiple first diodes and a first resistor positioned between the multiple first diodes. The circuit also comprises a second bandgap pair having multiple second diodes and a second resistor positioned between the multiple second diodes, the second bandgap pair being an inverted form of the first bandgap pair. The circuit further comprises a scaling resistor coupled to the first and second bandgap pairs. The circuit still further comprises an operational amplifier coupled to the first and second bandgap pairs.

Abstract: A voltage reference circuit includes a bandgap circuit and a temperature compensation circuit. The temperature compensation circuit includes a first trim circuit, a second trim circuit, and a resistive digital-to-analog converter. The resistive digital-to-analog converter is coupled to the first trim circuit, the second trim circuit, and the bandgap circuit. The resistive digital-to-analog converter is configured to generate a temperature compensation voltage, and to provide the temperature compensation voltage to the bandgap circuit.

Abstract: In some examples, a bandgap reference circuit comprises a first bandgap pair having multiple first diodes and a first resistor positioned between the multiple first diodes. The circuit also comprises a second bandgap pair having multiple second diodes and a second resistor positioned between the multiple second diodes, the second bandgap pair being an inverted form of the first bandgap pair. The circuit further comprises a scaling resistor coupled to the first and second bandgap pairs. The circuit still further comprises an operational amplifier coupled to the first and second bandgap pairs.

Abstract: A method and system for sub-circuit pattern recognition in integrated circuit design is disclosed. In one embodiment, a method for recognizing a pattern circuit in a target circuit, includes encoding the pattern circuit and the target circuit by processing a first netlist of the pattern circuit and a second netlist of the target circuit, generating a cross-linked data structure based on attributes and connectivity information of at least two devices and at least one net from the first netlist, and identifying an instance of the pattern circuit in the target circuit based on an associative mapping between the pattern circuit and a sub-circuit of the target circuit using a device integer array and a net integer array. Each of the first netlist and the second netlist is based on the at least two devices and the at least one net connecting the at least two devices.

Abstract: A method and system for sub-circuit pattern recognition in integrated circuit design is disclosed. In one embodiment, a method for recognizing a pattern circuit in a target circuit, includes encoding the pattern circuit and the target circuit by processing a first netlist of the pattern circuit and a second netlist of the target circuit, generating a cross-linked data structure based on attributes and connectivity information of at least two devices and at least one net from the first netlist, and identifying an instance of the pattern circuit in the target circuit based on an associative mapping between the pattern circuit and a sub-circuit of the target circuit using a device integer array and a net integer array. Each of the first netlist and the second netlist is based on the at least two devices and the at least one net connecting the at least two devices.