Patents by Inventor Sandeep Urgaonkar

Sandeep Urgaonkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230362734
    Abstract: This disclosure relates to techniques for performing wireless communications including filtering packets for transmission between a user equipment (UE) and a base station. Techniques for filtering packets using higher layer information, such as a flow identifier, are disclosed. A device may generate various tables and may use the tables to filter packets efficiently.
    Type: Application
    Filed: July 21, 2023
    Publication date: November 9, 2023
    Inventors: Martin Kugler, Vijay Venkataraman, Ahmed Soud Salem, Mathias Kohlenz, Sandeep Urgaonkar
  • Patent number: 11792690
    Abstract: This disclosure relates to techniques for performing wireless communications including filtering packets for transmission between a user equipment (UE) and a base station. Techniques for filtering packets using higher layer information, such as a flow identifier, are disclosed. A device may generate various tables and may use the tables to filter packets efficiently.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: October 17, 2023
    Assignee: Apple Inc.
    Inventors: Martin Kugler, Vijay Venkataraman, Ahmed Soud Salem, Mathias Kohlenz, Sandeep Urgaonkar
  • Publication number: 20230067498
    Abstract: This disclosure relates to techniques for performing wireless communications including filtering packets for transmission between a user equipment (UE) and a base station. Techniques for filtering packets using higher layer information, such as a flow identifier, are disclosed. A device may generate various tables and may use the tables to filter packets efficiently.
    Type: Application
    Filed: August 26, 2021
    Publication date: March 2, 2023
    Inventors: Martin Kugler, Vijay Venkataraman, Ahmed Soud Salem, Mathias Kohlenz, Sandeep Urgaonkar
  • Patent number: 10194337
    Abstract: Aspects of the present disclosure provide methods and apparatus for offloading checksum processing in a user equipment (UE) (e.g., from an application processor to a modem processor). Such offloading may speed up packet processing, increase data rate, and/or free up resources of the application processor for other tasks.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: January 29, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Amir Aminzadeh Gohari, Shailesh Maheshwari, Sandeep Urgaonkar, Alok Mitra, Mohammed M. Rumi, Vaibhav Kumar, Uppinder Singh Babbar, Thomas Klingenbrunn, Bao Vinh Nguyen, Mathias Kohlenz, Gautam Sheoran, Daisuke Terasawa, Iain Finlay
  • Patent number: 9038073
    Abstract: Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: May 19, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Mathias Kohlenz, Irfan Anwar Khan, Sathyanarayan Madhusudan, Shailesh Maheshwari, Srividhya Krishnamoorthy, Sandeep Urgaonkar, Thomas Klingenbrunn, Tim Tynghuei Liou, Idreas Mir
  • Patent number: 8788782
    Abstract: Multiple memory pools are defined in hardware for operating on data. At least one memory pool has a lower latency that the other memory pools. Hardware components operate directly on data in the lower latency memory pool.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: July 22, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Mathias Kohlenz, Idreas Mir, Irfan Anwar Khan, Sathyanarayan Madhusudan, Shailesh Maheshwari, Srividhya Krishnamoorthy, Sandeep Urgaonkar, Thomas Klingenbrunn, Tim Liou
  • Patent number: 8762532
    Abstract: Incoming data frames are parsed by a hardware component. Headers are extracted and stored in a first location along with a pointer to the associated payload. Payloads are stored in a single, contiguous memory location.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: June 24, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Mathias Kohlenz, Idreas Mir, Irfan Anwar Khan, Madhusudan Sathyanarayan, Shailesh Maheshwari, Srividhya Krishnamoorthy, Sandeep Urgaonkar, Thomas Klingenbrunn, Tim Tynghuei Liou
  • Publication number: 20140016550
    Abstract: Aspects of the present disclosure provide methods and apparatus for offloading checksum processing in a user equipment (UE) (e.g., from an application processor to a modem processor). Such offloading may speed up packet processing, increase data rate, and/or free up resources of the application processor for other tasks.
    Type: Application
    Filed: July 11, 2013
    Publication date: January 16, 2014
    Inventors: Amir Aminzadeh Gohari, Shailesh Maheshwari, Sandeep Urgaonkar, Alok Mitra, Mohammed M. Rumi, Vaibhav Kumar, Uppinder Singh Babbar, Thomas Klingenbrunn, Bao Vinh Nguyen, Mathias Kohlenz, Gautam Sheoran, Daisuke Terasawa, Iain Finlay
  • Publication number: 20110041128
    Abstract: An apparatus and method for distributed data processing is described herein. A main processor programs a mini-processor to process an incoming data stream. The mini-processor is located in close proximity to hardware components operating on the input data stream. A copy engine is also provided for copying data from multiple protocol data units in a single copy operation.
    Type: Application
    Filed: August 13, 2009
    Publication date: February 17, 2011
    Inventors: Mathias Kohlenz, Idreas Mir, Irfan Anwar Khan, Sathyanarayan Madhusudan, Shailesh Maheshwari, Srividhya Krishnamoorthy, Sandeep Urgaonkar, Thomas Klingenbrunn, Tim Tynghuei Liou
  • Publication number: 20110041127
    Abstract: Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.
    Type: Application
    Filed: August 13, 2009
    Publication date: February 17, 2011
    Inventors: Mathias Kohlenz, Irfan Anwar Khan, Sathyanarayan Madhusudan, Shailesh Maheshwari, Srividhya Krishnamoorthy, Sandeep Urgaonkar, Thomas Klingenbrunn, Tim Tynghuei Liou, Idreas Mir
  • Publication number: 20110040947
    Abstract: Multiple memory pools are defined in hardware for operating on data. At least one memory pool has a lower latency that the other memory pools. Hardware components operate directly on data in the lower latency memory pool.
    Type: Application
    Filed: August 13, 2009
    Publication date: February 17, 2011
    Inventors: Mathias Kohlenz, Idreas Mir, Irfan Anwar Khan, Sathyanarayanan Madhusudan, Shailesh Maheshwari, Srividhya Krishnamoorthy, Sandeep Urgaonkar, Thomas Klingenbrunn, Tim Tynghuei Liou
  • Publication number: 20110040948
    Abstract: Incoming data frames are parsed by a hardware component. Headers are extracted and stored in a first location along with a pointer to the associated payload. Payloads are stored in a single, contiguous memory location.
    Type: Application
    Filed: August 13, 2009
    Publication date: February 17, 2011
    Inventors: Mathias Kohlenz, Idreas Mir, Irfan Anwar Khan, Sathyanarayanan Medhusudan, Shailesh Maheshwari, Srividhya Krishnamoorthy, Sandeep Urgaonkar, Thomas Klingenbrunn, Tim Tynghuei Liou