Patents by Inventor Sandeep Vundavalli

Sandeep Vundavalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Glitch detector and test glitch generator
    Patent number: 10466275
    Abstract: Apparatus and associated methods relate to a glitch detection circuit monitoring a duration that a selected fractional supply voltage is below a predetermined voltage threshold. The selected fractional supply voltage may be at the predetermined threshold when the supply voltage is between a valid circuit-supply voltage and a power-on circuit-reset (POR). A glitch detect signal may be generated, for example, when the monitored duration is greater than a predetermined duration threshold. A test glitch generator may generate a test glitch, for example, having selectable voltage and duration, which may be selectably applied to the glitch detection circuit to verify operation.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: November 5, 2019
    Assignee: XILINX, INC.
    Inventors: Sandeep Vundavalli, Sree RKC Saraswatula, James D. Wesselkamper, Santosh Yachareni, Shidong Zhou, Anil Kumar Kandala
  • Delay chain having Schmitt triggers
    Patent number: 10069487
    Abstract: A disclosed delay circuit includes a plurality of Schmitt triggers that are serially coupled. A first Schmitt trigger of the plurality of Schmitt triggers is configured to receive an input signal. An output control circuit is coupled to receive output signals of two or more Schmitt triggers of the plurality of Schmitt triggers, the output control circuit configured to select a signal from one of the one or more Schmitt triggers as an output signal. The output signal is a delayed version of the input signal.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: September 4, 2018
    Assignee: XILINX, INC.
    Inventors: Anil Kumar Kandala, Santosh Yachareni, Sandeep Vundavalli, Vijay Kumar Koganti, Golla V S R K Prasad, Udaya Kumar Bobbili
  • System and method to reduce footprint and improve yield of fabric muxes in programmable logic devices
    Patent number: 9680474
    Abstract: An interconnect element includes: a selection circuit for receiving input signals and having a selection output; a half-latch circuit having an input coupled to the selection output, wherein the half latch circuit comprises a pull-up device; and a common bias circuit coupled to the pull-up device, wherein the common bias circuit is configured to supply a tunable bias voltage to the pull-up device.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: June 13, 2017
    Assignee: XILINX, INC.
    Inventors: Anil Kumar Kandala, Srinivasa L. Karumajji, Santosh Yachareni, Sandeep Vundavalli, Udaya Kumar Bobbili, Golla V S R K Prasad
  • Interconnect multiplexers and methods of reducing contention currents in an interconnect multiplexer
    Patent number: 9509307
    Abstract: An interconnect multiplexer comprises a plurality of CMOS pass gates of a first multiplexer stage coupled to receive data to be output by the interconnect multiplexer; an output inverter coupled to the outputs of the plurality of CMOS pass gates, wherein an output of the output inverter is an output of the interconnect multiplexer; and a plurality of memory elements coupled to the plurality of CMOS pass gates; wherein inputs to the plurality of CMOS pass gates are pulled to a common potential during a startup mode. A method of reducing contention currents in an integrated circuit is also disclosed.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: November 29, 2016
    Assignee: XILINX, INC.
    Inventors: Vikram Santurkar, Anil Kumar Kandala, Santosh Yachareni, Shidong Zhou, Robert Fu, Philip Costello, Sandeep Vundavalli, Steven P. Young, Brian C. Gaide