Patents by Inventor Sandeep Vusirikapally

Sandeep Vusirikapally has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and systems for reducing congestion in very large scale integrated (VLSI) chip design
    Patent number: 10169517
    Abstract: This disclosure relates generally to Very Large Scale Integrated (VLSI) chips and more particularly to methods and systems for reducing congestion in VLSI chip design. In one embodiment, a method includes applying a placement constraint with at least one hot-spot logic cell, wherein the placement constraint restricts placement of new logic cells within a predefined distance from each of the at least one hot-spot logic cell; applying a routing constraint on a metal layer in a node of the VLSI chip, wherein the node includes the at least one hot-spot logic cell; and restricting fresh placement of the post route database of the at least one hot-spot logic cell to original location extracted using feedback received after culmination of routing procedure while applying the placement constraint and the routing constraint.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: January 1, 2019
    Assignee: Wipro Limited
    Inventors: Narayanabhatla Satya Sridhar, Shashank Pal, Sandeep Vusirikapally, Nirosha Anumandla
  • Methods and Systems for Reducing Congestion in Very Large Scale Integrated (VLSI) Chip Design
    Publication number: 20170286585
    Abstract: This disclosure relates generally to Very Large Scale Integrated (VLSI) chips and more particularly to methods and systems for reducing congestion in VLSI chip design. In one embodiment, a method includes applying a placement constraint with at least one hot-spot logic cell, wherein the placement constraint restricts placement of new logic cells within a predefined distance from each of the at least one hot-spot logic cell; applying a routing constraint on a metal layer in a node of the VLSI chip, wherein the node includes the at least one hot-spot logic cell; and restricting fresh placement of the post route database of the at least one hot-spot logic cell to original location extracted using feedback received after culmination of routing procedure while applying the placement constraint and the routing constraint.
    Type: Application
    Filed: June 28, 2016
    Publication date: October 5, 2017
    Inventors: Narayanabhatla Satya SRIDHAR, Shashank Pal, Sandeep Vusirikapally, Nirosha Anumandla