Abstract: A controllable oscillator including an upper oscillator coupled between an upper supply voltage and an upper intermediate node that provides at least one upper oscillating signal on at least one upper oscillating node, a lower oscillator coupled between a lower intermediate node and a lower supply voltage that provides at least one lower oscillating signal on at least one lower oscillating node, an oscillation controller coupled between the upper and lower intermediate nodes, and amplification circuitry coupled between the upper and lower supply voltages, having at least one upper input coupled to the at least one upper oscillating node, having at least one lower input coupled to the at least one lower oscillating node, and having a primary output node for providing a primary rail-to-rail oscillation signal. A coupling circuit may be coupled between one or more upper and lower oscillating nodes for synchronization.

Abstract: Various embodiments relate to a free running oscillator, that includes a switch capacitor based frequency-to-voltage converter (F2V), a comparator, and a voltage controlled oscillator (VCO), which may be collectively configured to reduce amplifier offset and flicker noise while increasing effective gain of the amplifier of the comparator. The F2V may produce a feedback voltage Vfb corresponding to frequencies of output of the VCO. The comparator may be configured to sample a reference voltage Vref using a sampling capacitor, compare Vref to Vfb, and generate an output based on any difference between Vref and Vfb, where the output may be integrated using an integrating capacitor of the comparator. The comparator may compensate for parasitic capacitance at the output of the amplifier by using an amplifier having two outputs, with the sampling capacitor and integrating capacitor being coupled to respectively different outputs of the amplifier.

Abstract: Various embodiments relate to a free running oscillator, that includes a switch capacitor based frequency-to-voltage converter (F2V), a comparator, and a voltage controlled oscillator (VCO), which may be collectively configured to reduce amplifier offset and flicker noise while increasing effective gain of the amplifier of the comparator. The F2V may produce a feedback voltage Vfb corresponding to frequencies of output of the VCO. The comparator may be configured to sample a reference voltage Vref using a sampling capacitor, compare Vref to Vfb, and generate an output based on any difference between Vref and Vfb, where the output may be integrated using an integrating capacitor of the comparator. The comparator may compensate for parasitic capacitance at the output of the amplifier by using an amplifier having two outputs, with the sampling capacitor and integrating capacitor being coupled to respectively different outputs of the amplifier.

Abstract: Various embodiments relate to a free running oscillator, including: a voltage controlled oscillator circuit including an input configured to receive an input voltage and an output configured to provide an oscillation signal, wherein the input voltage controls a frequency of the oscillation signal; a frequency to voltage circuit including an input configured to receive the oscillation signal and an output configured to produce a voltage dependent on a frequency of the oscillation signal; a comparison circuit including an input and an output comprising: a first amplifier including a first input, a second input, and an output, wherein the output is based upon a difference in voltage between the first input and the second input, wherein the first input received one of a reference voltage and the output of frequency to voltage circuit; a second amplifier including a first input, a second input, and an output, wherein the output is based upon a difference in voltage between the first input and the second input, fir

Abstract: There is disclosed an apparatus comprising a first phase-locked loop comprising: a phase detector (302, 304), arranged to receive a reference clock signal (306) and a feedback clock signal (308) and to output a frequency control signal based on a phase difference between the reference clock signal (306) and the feedback clock signal (308); a variable-frequency oscillator (312, 314) arranged to output an oscillator signal having a frequency dependent on said frequency control signal; first divider circuitry (316) for generating said feedback clock signal (308) by frequency-dividing said oscillator signal; and second divider circuitry (320) for generating an output clock signal (3220 by frequency-dividing said oscillator signal; wherein a phase relation between said first divider circuitry (316) and said second divider circuitry (320) is adjustable to delay or advance said output clock signal (322) relative to said feedback clock signal (308). The apparatus may be a radar receiver or transceiver.

Abstract: There is disclosed an apparatus comprising a first phase-locked loop comprising: a phase detector (302, 304), arranged to receive a reference clock signal (306) and a feedback clock signal (308) and to output a frequency control signal based on a phase difference between the reference clock signal (306) and the feedback clock signal (308); a variable-frequency oscillator (312, 314) arranged to output an oscillator signal having a frequency dependent on said frequency control signal; first divider circuitry (316) for generating said feedback clock signal (308) by frequency-dividing said oscillator signal; and second divider circuitry (320) for generating an output clock signal (3220 by frequency-dividing said oscillator signal; wherein a phase relation between said first divider circuitry (316) and said second divider circuitry (320) is adjustable to delay or advance said output clock signal (322) relative to said feedback clock signal (308). The apparatus may be a radar receiver or transceiver.

Abstract: An oscillator system includes a voltage controlled oscillator (VCO) circuit. The VCO circuit includes an output for providing an oscillation signal and input to receive a voltage that controls the frequency of the oscillation signal. The oscillator system includes a frequency to voltage circuit that receives the oscillation signal and produces a voltage that is dependent upon the frequency of the oscillation signal. The oscillator system includes a comparison circuit including an amplifier. The amplifier includes an inverting input, a non inverting input, and an output. During a first phase of the comparison circuit, the non inverting input receives a reference voltage and the inverting input is coupled to the output of the amplifier via a switch and to a capacitor wherein the capacitor samples the voltage of the output.

Abstract: An oscillator system includes a voltage controlled oscillator (VCO) circuit. The VCO circuit includes an output for providing an oscillation signal and input to receive a voltage that controls the frequency of the oscillation signal. The oscillator system includes a frequency to voltage circuit that receives the oscillation signal and produces a voltage that is dependent upon the frequency of the oscillation signal. The oscillator system includes a comparison circuit including an amplifier. The amplifier includes an inverting input, a non inverting input, and an output. During a first phase of the comparison circuit, the non inverting input receives a reference voltage and the inverting input is coupled to the output of the amplifier via a switch and to a capacitor wherein the capacitor samples the voltage of the output.

Abstract: A DC-DC converter is provided with a first estimator unit (RAE, RLPF, RHPF) for performing an accurate control signal estimation and a second estimator unit (FEU, ?VEU) for performing a fast control signal estimation. In addition, a switching unit (SU) is provided for switching to an output of the first estimator unit (RAE, RLPF, RHPF) during almost constant control signal conditions and for switching to an output of the second estimator unit (FEU, ?VEU) during changing control signal conditions to provide an estimation on the required control signal.

Abstract: A DC-DC converter is provided with a first estimator unit (RAE, RLPF, RHPF) for performing an accurate control signal estimation and a second estimator unit (FEU, ?VEU) for performing a fast control signal estimation. In addition, a switching unit (SU) is provided for switching to an output of the first estimator unit (RAE, RLPF, RHPF) during almost constant control signal conditions and for switching to an output of the second estimator unit (FEU, ?VEU) during changing control signal conditions to provide an estimation on the required control signal.

Abstract: Disclosed is an energy recovery device for recovering energy in a display panel, in particular a plasma display panel, wherein an energy recovery storing unit (Lrecover) is coupled with the display panel during an energy recovery period following a sustain period. The particularity of the invention is that the energy recovery recover storing unit (Lrecover) is charged in said sustain step.

Abstract: A three electrode PDP comprises a scan driver (SD) which supplies a substantially sine wave shaped voltage (VS) between first and the second scan electrodes (SEi, CEi), an amplitude of the substantially sine wave shaped voltage (VS) being large enough to sustain plasma cells (PCij), but being too small to ignite the plasma cells (PCij). A data driver (DD) supplies a substantially pulse shaped voltage (VD) to the data electrodes (DEi) for controlling an amount of light produced by the plasma cells (PCij). The sine wave shaped voltage may have a predetermined frequency such that more than one stable light output level is obtained.

Abstract: The present invention provides for a matrix display device (10) and related method of controlling light output from such a device employing sub-field addressing (14) and comprising determining the display load of the device (10), and further including the steps of dynamically varying the number of sub-fields available for display of an image responsive to said display load being determined (16) to be below a threshold value and advantageously employing partial line doubling and/or dithering (22,24) for at least the least significant bits of the display signal.

Abstract: A display device comprises groups of scan electrodes (X1, X2) and groups of sustain electrodes (Y1-Y2) forming groups of electrode pairs (X1-Y1, X1-Y2, X2-Y1, X2-Y2). The sustain discharge for at least one of these groups occur at a different time than for at least one other group. The currents during sustain discharge are then distributed in time, reducing the peak heights and reducing losses and stray electromagnetic radiation.