Patents by Inventor Sandhya Chandrashekhar

Sandhya Chandrashekhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230170424
    Abstract: This document describes electromagnetic radiation (EMR) transmissive polymer substrates and techniques for producing EMR transmissive polymer substrates by pre-treating polymer substrates with at least one lipid. In aspects, the EMR transmissive polymer substrates are infrared (IR) transmissive polymer substrates and the techniques described are for producing IR transmissive polymer substrates. In general, disclosed techniques include applying a coating of at least one lipid to at least one surface of a polymer substrate and then performing a heat-treatment process on the coated polymer substrate. The techniques may also include performing a cooling process on the polymer substrate after the heat-treatment process.
    Type: Application
    Filed: January 26, 2023
    Publication date: June 1, 2023
    Applicant: Google LLC
    Inventors: Sandhya Chandrashekhar, Samuel Wei Sheng, Jean-Marie Bussat, Yoo Hsiu Yeh, Khozema Jafferji
  • Patent number: 10319732
    Abstract: In sophisticated SOI transistor elements, the buried insulating layer may be specifically engineered so as to include non-standard dielectric materials. For instance, a charge-trapping material and/or a high-k dielectric material and/or a ferroelectric material may be incorporated into the buried insulating layer. In this manner, non-volatile storage transistor elements with superior performance may be obtained and/or efficiency of a back-bias mechanism may be improved.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: June 11, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Jochen Willi. Poth, Sven Beyer, Stefan Duenkel, Sandhya Chandrashekhar, Zhi-Yuan Wu
  • Publication number: 20180366484
    Abstract: In sophisticated SOI transistor elements, the buried insulating layer may be specifically engineered so as to include non-standard dielectric materials. For instance, a charge-trapping material and/or a high-k dielectric material and/or a ferroelectric material may be incorporated into the buried insulating layer. In this manner, non-volatile storage transistor elements with superior performance may be obtained and/or efficiency of a back-bias mechanism may be improved.
    Type: Application
    Filed: June 14, 2017
    Publication date: December 20, 2018
    Inventors: Ralf Richter, Jochen Willi. Poth, Sven Beyer, Stefan Duenkel, Sandhya Chandrashekhar, Zhi-Yuan Wu