Patents by Inventor Sandhya Viswanathan

Sandhya Viswanathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10120731
    Abstract: Various embodiments are generally directed to techniques for controlling the use of locks that regulate access to shared resources by concurrently executed portions of code. An apparatus to control locking of a resource includes a processor component, a history analyzer for execution by the processor component to analyze at least one result of a replacement of a lock instruction of a first instance of code with a lock marker to allow the processor component to speculatively execute a second instance of code, and a locking component for execution by the processor component to replace the lock instruction with the lock marker based on analysis of the at least one result, the first and second instances of code to access a resource and the lock instruction to request a lock of access to the resource to the first instance of code. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: November 6, 2018
    Assignee: INTEL CORPORATION
    Inventors: Khun Ban, Kingsum Chow, Shirish Aundhe, Sandhya Viswanathan
  • Publication number: 20180095892
    Abstract: A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate source memory address information, and the instruction to indicate a destination architecturally-visible storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to store a result in the destination architecturally-visible storage location. The result is to include one of: (1) a page group identifier that is to correspond to a logical memory address that is to be based, at least in part, on the source memory address information; and (2) a set of page group metadata that is to correspond to the page group identifier. Other processors, methods, systems, and instructions are disclosed.
    Type: Application
    Filed: October 1, 2016
    Publication date: April 5, 2018
    Applicant: Intel Corporation
    Inventors: Hugh Wilkinson, William R. Wheeler, Shirish Aundhe, Sandhya Viswanathan, David A. Koufaty
  • Publication number: 20150220372
    Abstract: Various embodiments are generally directed to techniques for controlling the use of locks that regulate access to shared resources by concurrently executed portions of code. An apparatus to control locking of a resource includes a processor component, a history analyzer for execution by the processor component to analyze at least one result of a replacement of a lock instruction of a first instance of code with a lock marker to allow the processor component to speculatively execute a second instance of code, and a locking component for execution by the processor component to replace the lock instruction with the lock marker based on analysis of the at least one result, the first and second instances of code to access a resource and the lock instruction to request a lock of access to the resource to the first instance of code. Other embodiments are described and claimed.
    Type: Application
    Filed: July 15, 2013
    Publication date: August 6, 2015
    Inventors: Khun Ban, Kingsum Chow, Shirish Aundhe, Sandhya Viswanathan