Patents by Inventor Sandip Bag

Sandip Bag has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7797650
    Abstract: A system and method for re-executing a test case and modifying the test case's effective addresses, effective segment identifiers (ESIDs), and virtual segment identifiers (VSIDs) in order to fully test a processor's SLB and TLB cells is presented. A test case generator generates a test case that includes an initial set of test case effective addresses, an initial set of ESIDs, and an initial set of VSIDs. The test case executor uses an effective address arithmetic function and a virtual address arithmetic function to modify the test case effective addresses, the ESIDs, and the VSIDs on each re-execution that, in turn, sets/unsets each bit within each SLB and TLB entry. In one embodiment, the invention described herein sequentially shifts segment lookaside buffer entries, whose ESIDs are in single bit increments, in order to fully test each ESID bit location within each SLB entry.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: September 14, 2010
    Assignee: International Business Machines Corporation
    Inventors: Sandip Bag, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Batchu Naga Venkata Satyanarayana
  • Patent number: 7739570
    Abstract: A system and method to reduce verification time by sharing memory between multiple test patterns and performing results checking after each test pattern executes one time is presented. A test pattern generator generates multiple test pattern sets, each of which including multiple test patterns. Each test pattern set is executed by a corresponding thread/processor until each test pattern included in the test pattern set has executed at least once. After all test patterns have executed at least once, a test pattern executor performs a memory error detection check to determine whether the system is functioning correctly. Since the invention described herein waits until all test patterns have executed before performing a memory error detection check, less time is spent on memory error detection checks, which allows more time to execute test patterns.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: June 15, 2010
    Assignee: International Business Machines Corporation
    Inventors: Sandip Bag, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Rahul Sharad Moharil
  • Patent number: 7669083
    Abstract: A system and method for creating multiple test case scenarios from one test case by shuffling the test case instruction order while maintaining relative sub test case instruction order intact is presented. A test case generator generates and provides a test case that includes multiple sub test cases to a test case executor. In turn, the test case executor recursively schedules and dispatches the test case with different shuffled instruction orders to a processor in order to efficiently test the processor. In one embodiment, the test case generator provides multiple test cases to the test case executor. In another embodiment, the test case generator provides test cases to multiple test case executors that, in turn, shuffle the test cases and provide the shuffled test cases to their respective processor.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: February 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Sampan Arora, Sandip Bag, Vinod Bussa, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Batchu Naga Venkata Satyanarayana, Shiraz Mohammad Zaman
  • Patent number: 7584394
    Abstract: A system and method for pseudo-randomly allocating page table memory for test pattern instructions to produce complex test scenarios during processor execution is presented. The invention described herein distributes page table memory across processors and across multiple test patterns, such as when a processor executes “n” test patterns. In addition, the page table memory is allocated using a “true” sharing mode or a “false” sharing mode. The false sharing mode provides flexibility of performing error detection checks on the test pattern results. In addition, since a processor comprises sub units such as a cache, a TLB (translation look aside buffer), an SLB (segment look aside buffer), an MMU (memory management unit), and data/instruction pre-fetch engines, the test patterns effectively use the page table memory to test each of the sub units.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: September 1, 2009
    Assignee: International Business Machines Corporation
    Inventors: Shubhodeep Roy Choudhury, Sandip Bag, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Bhavani Shringari Nanjundiah
  • Publication number: 20090070631
    Abstract: A system and method for creating multiple test case scenarios from one test case by shuffling the test case instruction order while maintaining relative sub test case instruction order intact is presented. A test case generator generates and provides a test case that includes multiple sub test cases to a test case executor. In turn, the test case executor recursively schedules and dispatches the test case with different shuffled instruction orders to a processor in order to efficiently test the processor. In one embodiment, the test case generator provides multiple test cases to the test case executor. In another embodiment, the test case generator provides test cases to multiple test case executors that, in turn, shuffle the test cases and provide the shuffled test cases to their respective processor.
    Type: Application
    Filed: September 11, 2007
    Publication date: March 12, 2009
    Inventors: Sampan Arora, Sandip Bag, Vinod Bussa, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Batchu Naga Venkata Satyanarayana, Shiraz Mohammad Zaman
  • Publication number: 20090070632
    Abstract: A system and method for re-executing a test case and modifying the test case's effective addresses, effective segment identifiers (ESIDs), and virtual segment identifiers (VSIDs) in order to fully test a processor's SLB and TLB cells is presented. A test case generator generates a test case that includes an initial set of test case effective addresses, an initial set of ESIDs, and an initial set of VSIDs. The test case executor uses an effective address arithmetic function and a virtual address arithmetic function to modify the test case effective addresses, the ESIDs, and the VSIDs on each re-execution that, in turn, sets/unsets each bit within each SLB and TLB entry. In one embodiment, the invention described herein sequentially shifts segment lookaside buffer entries, whose ESIDs are in single bit increments, in order to fully test each ESID bit location within each SLB entry.
    Type: Application
    Filed: September 11, 2007
    Publication date: March 12, 2009
    Inventors: Sandip Bag, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Batchu Naga Venkata Satyanarayana
  • Publication number: 20090024873
    Abstract: A system and method to reduce verification time by sharing memory between multiple test patterns and performing results checking after each test pattern executes one time is presented. A test pattern generator generates multiple test pattern sets, each of which including multiple test patterns. Each test pattern set is executed by a corresponding thread/processor until each test pattern included in the test pattern set has executed at least once. After all test patterns have executed at least once, a test pattern executor performs a memory error detection check to determine whether the system is functioning correctly. Since the invention described herein waits until all test patterns have executed before performing a memory error detection check, less time is spent on memory error detection checks, which allows more time to execute test patterns.
    Type: Application
    Filed: July 18, 2007
    Publication date: January 22, 2009
    Inventors: Sandip Bag, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Rahul Sharad Moharil
  • Publication number: 20090024891
    Abstract: A system and method for pseudo-randomly allocating page table memory for test pattern instructions to produce complex test scenarios during processor execution is presented. The invention described herein distributes page table memory across processors and across multiple test patterns, such as when a processor executes “n” test patterns. In addition, the page table memory is allocated using a “true” sharing mode or a “false” sharing mode. The false sharing mode provides flexibility of performing error detection checks on the test pattern results. In addition, since a processor comprises sub units such as a cache, a TLB (translation look aside buffer), an SLB (segment look aside buffer), an MMU (memory management unit), and data/instruction pre-fetch engines, the test patterns effectively use the page table memory to test each of the sub units.
    Type: Application
    Filed: July 18, 2007
    Publication date: January 22, 2009
    Inventors: Shubhodeep Roy Choudhury, Sandip Bag, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Bhavani Shringari Nanjundiah