Abstract: The present invention relates to a consumer product comprising a laminate packaging comprising an outer oriented multilayer film comprising a polyolefin-based polymer; an inner multilayer film comprising a polyolefin-based polymer; and a composition comprising 0.2% to 1.2% by weight of a perfume; wherein the outer and the inner layers are made of the same polyolefin-based polymer, which is ethylene based polymer or propylene based polymer; and wherein the composition is packaged inside the laminate packaging.

Abstract: The present invention has for its object to provide an adhesive composition that is based on a naturally occurring material less likely to have adverse influences on the human body and has a tensile shear strength (adhesive strength) of at least 1 MPa with respect to a variety of adherends. The present invention provides an adhesive composition including at least a first pack and a second pack, wherein the first pack contains a tannic acid derivative in which a hydrogen atom in at least some hydroxyl group of tannic acid is substituted by a chain hydrocarbon group having at least one hydroxyl group, and the second pack contains a hydrocarbon having at least two cyanate groups or a derivative of the hydrocarbon.

Abstract: The present invention has for its object to provide an adhesive composition that is based on a naturally occurring material less likely to have adverse influences on the human body and has a tensile shear strength (adhesive strength) of at least 1 MPa with respect to a variety of adherends. The present invention provides an adhesive composition including at least a first pack and a second pack, wherein the first pack contains a tannic acid derivative in which a hydrogen atom in at least some hydroxyl group of tannic acid is substituted by a chain hydrocarbon group having at least one hydroxyl group, and the second pack contains a hydrocarbon having at least two cyanate groups or a derivative of the hydrocarbon.

Abstract: A system and method for data replication for databases using an intermediary server, the intermediary server choosing the order in which databases are replicated, the utilities used for each of the steps in the data replication process, the timing of the replication, and/or the timing each step of the data replication process is performed.

Abstract: An aspect of the present disclosure provides a hardware element in a Network on Chip (NoC), wherein the hardware element includes a clock gating circuit configures one or more neighboring hardware elements to activate before receiving new incoming data and to sleep after a defined number of cycles, wherein the defined number of cycles can be counted from a cycle having non-receipt of incoming data and/or having a clearance of all data within an input queue of a source hardware element.

Abstract: An aspect of the present disclosure provides a hardware element in a Network on Chip (NoC), wherein the hardware element includes a clock gating circuit configures one or more neighboring hardware elements to activate before receiving new incoming data and to sleep after a defined number of cycles, wherein the defined number of cycles can be counted from a cycle having non-receipt of incoming data and/or having a clearance of all data within an input queue of a source hardware element.

Abstract: An aspect of the present disclosure provides a hardware element in a Network on Chip (NoC), wherein the hardware element includes a clock gating circuit configures one or more neighboring hardware elements to activate before receiving new incoming data and to sleep after a defined number of cycles, wherein the defined number of cycles can be counted from a cycle having non-receipt of incoming data and/or having a clearance of all data within an input queue of a source hardware element.

Abstract: A system and method for data replication for databases using an intermediary server, the intermediary server choosing the order in which databases are replicated, the utilities used for each of the steps in the data replication process, the timing of the replication, and/or the timing each step of the data replication process is performed.

Abstract: An aspect of the present disclosure provides a hardware element in a Network on Chip (NoC), wherein the hardware element includes a clock gating circuit configures one or more neighboring hardware elements to activate before receiving new incoming data and to sleep after a defined number of cycles, wherein the defined number of cycles can be counted from a cycle having non-receipt of incoming data and/or having a clearance of all data within an input queue of a source hardware element.

Abstract: A processor may include several processor cores, each including a respective higher-level cache, wherein each higher-level cache includes higher-level cache lines; and a lower-level cache including lower-level cache lines, where each of the lower-level cache lines may be configured to store data that corresponds to multiple higher-level cache lines. In response to invalidating a given lower-level cache line, the lower-level cache may be configured to convey a sequence including several invalidation packets to the processor cores via an interface, where each member of the sequence of invalidation packets corresponds to a respective higher-level cache line to be invalidated, and where the interface is narrower than an interface capable of concurrently conveying all invalidation information corresponding to the given lower-level cache line. Each invalidation packet may include invalidation information indicative of a location of the respective higher-level cache line within different ones of the processor cores.

Abstract: A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers in a given tag unit may share access to a resource that may include one or more of an interconnect egress port coupled to the interconnect network, an interconnect ingress port coupled to the interconnect network, a test controller, or a data storage structure.

Abstract: A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers in a given tag unit may share access to a resource that may include one or more of an interconnect egress port coupled to the interconnect network, an interconnect ingress port coupled to the interconnect network, a test controller, or a data storage structure.

Abstract: A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers may share access to an interconnect egress port coupled to the interconnect network, and may generate multiple concurrent requests to convey data via the shared port, where each of the requests is destined for a corresponding core, and where a datapath width of the port is less than a combined width of the multiple requests. The given tag unit may arbitrate among the controllers for access to the shared port, such that the requests are transmitted to corresponding cores serially rather than concurrently.

Abstract: A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers may share access to an interconnect egress port coupled to the interconnect network, and may generate multiple concurrent requests to convey data via the shared port, where each of the requests is destined for a corresponding core, and where a datapath width of the port is less than a combined width of the multiple requests. The given tag unit may arbitrate among the controllers for access to the shared port, such that the requests are transmitted to corresponding cores serially rather than concurrently.

Abstract: A processor may include several processor cores, each including a respective higher-level cache, wherein each higher-level cache includes higher-level cache lines; and a lower-level cache including lower-level cache lines, where each of the lower-level cache lines may be configured to store data that corresponds to multiple higher-level cache lines. In response to invalidating a given lower-level cache line, the lower-level cache may be configured to convey a sequence including several invalidation packets to the processor cores via an interface, where each member of the sequence of invalidation packets corresponds to a respective higher-level cache line to be invalidated, and where the interface is narrower than an interface capable of concurrently conveying all invalidation information corresponding to the given lower-level cache line. Each invalidation packet may include invalidation information indicative of a location of the respective higher-level cache line within different ones of the processor cores.

Abstract: Disclosed is a method and apparatus to provide for fingerprint minutiae matching using scoring techniques. A plurality of minutiae in a fingerprint image is defined. A score associated with each minutia corresponding to the validity of each minutia is estimated. The fingerprint image is then matched against one or more sample fingerprint images utilizing a partial point set pattern matching (PSPM) algorithm.

Abstract: Disclosed is a method and apparatus to provide for fingerprint minutiae matching using scoring techniques. A plurality of minutiae in a fingerprint image is defined. A score associated with each minutia corresponding to the validity of each minutia is estimated. The fingerprint image is then matched against one or more sample fingerprint images utilizing a partial point set pattern matching (PSPM) algorithm.

Abstract: A system and method for data replication for databases using an intermediary server, the intermediary server choosing the order in which databases are replicated, the utilities used for each of the steps in the data replication process, the timing of the replication, and/or the timing each step of the data replication process is performed.