Abstract: An apparatus, system, and method for arbitrating for a serial bus in an efficient manner. An arbitration phase includes master devices asserting respective arbitration addresses on the serial bus after initiating communications sequences with a START condition. After the arbitration phase, the controlling master device conveys a data transfer upon the serial bus. The serial bus and the devices connected thereto may operate according to an I2C-compatable protocol. The arbitration address may correspond to a slave address associated with a slave device. Each arbitration address is preferably associated with only one master device. The arbitration address preferably initiates a READ cycle, and the slave device responds with a data byte. The data byte may be stored, discarded, or ignored by the master device, as desired. The arbitration address may not be associated with any slave device coupled to the serial bus.